| spear6xx_clock.c (db8c246937713e60b7628661ccc187eeb81f2bae) | spear6xx_clock.c (df2449aba4749fb8d04c3c1bbfad5cf8863c323b) |
|---|---|
| 1/* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any --- 247 unchanged lines hidden (view full) --- 256 257 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 258 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 259 clk_register_clkdev(clk, NULL, "gpt3"); 260 261 /* clock derived from pll3 clk */ 262 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 263 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); | 1/* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any --- 247 unchanged lines hidden (view full) --- 256 257 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 258 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 259 clk_register_clkdev(clk, NULL, "gpt3"); 260 261 /* clock derived from pll3 clk */ 262 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 263 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); |
| 264 clk_register_clkdev(clk, NULL, "usbh.0_clk"); | 264 clk_register_clkdev(clk, NULL, "e1800000.ehci"); 265 clk_register_clkdev(clk, NULL, "e1900000.ohci"); |
| 265 266 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 267 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); | 266 267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 268 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); |
| 268 clk_register_clkdev(clk, NULL, "usbh.1_clk"); | 269 clk_register_clkdev(clk, NULL, "e2000000.ehci"); 270 clk_register_clkdev(clk, NULL, "e2100000.ohci"); |
| 269 270 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 271 USBD_CLK_ENB, 0, &_lock); 272 clk_register_clkdev(clk, NULL, "designware_udc"); 273 274 /* clock derived from ahb clk */ 275 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 276 1); --- 64 unchanged lines hidden --- | 271 272 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 273 USBD_CLK_ENB, 0, &_lock); 274 clk_register_clkdev(clk, NULL, "designware_udc"); 275 276 /* clock derived from ahb clk */ 277 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 278 1); --- 64 unchanged lines hidden --- |