spear3xx_clock.c (e5451c8f8330e03ad3cfa16048b4daf961af434f) spear3xx_clock.c (afb4bdc9d8987eb570ef0e9e608459d9fc016de5)
1/*
2 * SPEAr3xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <vireshk@kernel.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any

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246static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
247
248static void __init spear320_clk_init(void __iomem *soc_config_base,
249 struct clk *ras_apb_clk)
250{
251 struct clk *clk;
252
253 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
1/*
2 * SPEAr3xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <vireshk@kernel.org>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any

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246static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
247
248static void __init spear320_clk_init(void __iomem *soc_config_base,
249 struct clk *ras_apb_clk)
250{
251 struct clk *clk;
252
253 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
254 CLK_IS_ROOT, 125000000);
254 0, 125000000);
255 clk_register_clkdev(clk, "smii_125m_pad", NULL);
256
257 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
258 1, 1);
259 clk_register_clkdev(clk, NULL, "90000000.clcd");
260
261 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
262 1);

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386#else
387static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
388#endif
389
390void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
391{
392 struct clk *clk, *clk1, *ras_apb_clk;
393
255 clk_register_clkdev(clk, "smii_125m_pad", NULL);
256
257 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
258 1, 1);
259 clk_register_clkdev(clk, NULL, "90000000.clcd");
260
261 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
262 1);

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386#else
387static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
388#endif
389
390void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
391{
392 struct clk *clk, *clk1, *ras_apb_clk;
393
394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
395 32000);
394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
396 clk_register_clkdev(clk, "osc_32k_clk", NULL);
397
395 clk_register_clkdev(clk, "osc_32k_clk", NULL);
396
398 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
399 24000000);
397 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
400 clk_register_clkdev(clk, "osc_24m_clk", NULL);
401
402 /* clock derived from 32 KHz osc clk */
403 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
404 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
405 clk_register_clkdev(clk, NULL, "fc900000.rtc");
406
407 /* clock derived from 24 MHz osc clk */

--- 262 unchanged lines hidden --- 		398 clk_register_clkdev(clk, "osc_24m_clk", NULL);
399
400 /* clock derived from 32 KHz osc clk */
401 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
402 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
403 clk_register_clkdev(clk, NULL, "fc900000.rtc");
404
405 /* clock derived from 24 MHz osc clk */

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