spear1340_clock.c (e3900e74f26fc924c8e9e2a922bd40369b0bb517) spear1340_clock.c (d9909ebe650f028459b9be5a2321fee520b446b0)
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* Clock Configuration Registers */
20#include "clk.h"
21
22/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
23#define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29
30/* PLL related registers and bit values */
24 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
25 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
26 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
27 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
28
29/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
30#define SPEAR1340_PLL_CFG (misc_base + 0x210)
32 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38 #define SPEAR1340_PLL_CLK_MASK 2
39 #define SPEAR1340_PLL3_CLK_SHIFT 24
40 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20
42
31 /* PLL_CFG bit values */
32 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
33 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
34 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
35 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
36 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
37 #define SPEAR1340_PLL_CLK_MASK 2
38 #define SPEAR1340_PLL3_CLK_SHIFT 24
39 #define SPEAR1340_PLL2_CLK_SHIFT 22
40 #define SPEAR1340_PLL1_CLK_SHIFT 20
41
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
42#define SPEAR1340_PLL1_CTR (misc_base + 0x214)
43#define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
44#define SPEAR1340_PLL2_CTR (misc_base + 0x220)
45#define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
46#define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
47#define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
48#define SPEAR1340_PLL4_CTR (misc_base + 0x238)
49#define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
50#define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
52 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56 #define SPEAR1340_GPT3_CLK_SHIFT 13
57 #define SPEAR1340_GPT2_CLK_SHIFT 12
58 #define SPEAR1340_GPT_CLK_MASK 1
59 #define SPEAR1340_GPT1_CLK_SHIFT 9
60 #define SPEAR1340_GPT0_CLK_SHIFT 8
61 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_UART1_CLK_SHIFT 6
63 #define SPEAR1340_UART0_CLK_SHIFT 4
64 #define SPEAR1340_CLCD_CLK_MASK 2
65 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1
68
51 /* PERIP_CLK_CFG bit values */
52 #define SPEAR1340_SPDIF_CLK_MASK 1
53 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
54 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
55 #define SPEAR1340_GPT3_CLK_SHIFT 13
56 #define SPEAR1340_GPT2_CLK_SHIFT 12
57 #define SPEAR1340_GPT_CLK_MASK 1
58 #define SPEAR1340_GPT1_CLK_SHIFT 9
59 #define SPEAR1340_GPT0_CLK_SHIFT 8
60 #define SPEAR1340_UART_CLK_MASK 2
61 #define SPEAR1340_UART1_CLK_SHIFT 6
62 #define SPEAR1340_UART0_CLK_SHIFT 4
63 #define SPEAR1340_CLCD_CLK_MASK 2
64 #define SPEAR1340_CLCD_CLK_SHIFT 2
65 #define SPEAR1340_C3_CLK_MASK 1
66 #define SPEAR1340_C3_CLK_SHIFT 1
67
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
68#define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74
69 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
70 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
71 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
73
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
74#define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1340_I2S_REF_SEL_MASK 1
89 #define SPEAR1340_I2S_REF_SHIFT 2
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92
75 /* I2S_CLK_CFG register mask */
76 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
77 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
78 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
79 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
80 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
81 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
82 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
83 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
84 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
85 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
86 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
87 #define SPEAR1340_I2S_REF_SEL_MASK 1
88 #define SPEAR1340_I2S_REF_SHIFT 2
89 #define SPEAR1340_I2S_SRC_CLK_MASK 2
90 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
91
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
92#define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
93#define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
94#define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
95#define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
96#define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
97#define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
98#define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
99#define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
100#define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
101#define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
102#define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
103#define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
104#define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
105#define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
106#define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29
111 #define SPEAR1340_CLCD_CLK_ENB 27
112 #define SPEAR1340_DMA_CLK_ENB 25
113 #define SPEAR1340_GPIO1_CLK_ENB 24
114 #define SPEAR1340_GPIO0_CLK_ENB 23
115 #define SPEAR1340_GPT1_CLK_ENB 22

--- 12 unchanged lines hidden (view full) ---

128 #define SPEAR1340_SDHCI_CLK_ENB 6
129 #define SPEAR1340_SMI_CLK_ENB 5
130 #define SPEAR1340_FSMC_CLK_ENB 4
131 #define SPEAR1340_SYSRAM0_CLK_ENB 3
132 #define SPEAR1340_SYSRAM1_CLK_ENB 2
133 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0
135
107 #define SPEAR1340_RTC_CLK_ENB 31
108 #define SPEAR1340_ADC_CLK_ENB 30
109 #define SPEAR1340_C3_CLK_ENB 29
110 #define SPEAR1340_CLCD_CLK_ENB 27
111 #define SPEAR1340_DMA_CLK_ENB 25
112 #define SPEAR1340_GPIO1_CLK_ENB 24
113 #define SPEAR1340_GPIO0_CLK_ENB 23
114 #define SPEAR1340_GPT1_CLK_ENB 22

--- 12 unchanged lines hidden (view full) ---

127 #define SPEAR1340_SDHCI_CLK_ENB 6
128 #define SPEAR1340_SMI_CLK_ENB 5
129 #define SPEAR1340_FSMC_CLK_ENB 4
130 #define SPEAR1340_SYSRAM0_CLK_ENB 3
131 #define SPEAR1340_SYSRAM1_CLK_ENB 2
132 #define SPEAR1340_SYSROM_CLK_ENB 1
133 #define SPEAR1340_BUS_CLK_ENB 0
134
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
135#define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6
140 #define SPEAR1340_GPT3_CLK_ENB 5
141 #define SPEAR1340_GPT2_CLK_ENB 4
142 #define SPEAR1340_KBD_CLK_ENB 3
143 #define SPEAR1340_CPU_DBG_CLK_ENB 2
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146
136 #define SPEAR1340_THSENS_CLK_ENB 8
137 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
138 #define SPEAR1340_ACP_CLK_ENB 6
139 #define SPEAR1340_GPT3_CLK_ENB 5
140 #define SPEAR1340_GPT2_CLK_ENB 4
141 #define SPEAR1340_KBD_CLK_ENB 3
142 #define SPEAR1340_CPU_DBG_CLK_ENB 2
143 #define SPEAR1340_DDR_CORE_CLK_ENB 1
144 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
145
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
146#define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154 #define SPEAR1340_CAM0_CLK_ENB 10
155 #define SPEAR1340_CAM1_CLK_ENB 9

--- 280 unchanged lines hidden (view full) ---

436static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
437static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
438
439static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
440 "pll3_clk", };
441static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
442 "pll2_clk", };
443
147 #define SPEAR1340_PLGPIO_CLK_ENB 18
148 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
149 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
150 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
151 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
152 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
153 #define SPEAR1340_CAM0_CLK_ENB 10
154 #define SPEAR1340_CAM1_CLK_ENB 9

--- 280 unchanged lines hidden (view full) ---

435static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
436static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
437
438static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
439 "pll3_clk", };
440static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
441 "pll2_clk", };
442
444void __init spear1340_clk_init(void)
443void __init spear1340_clk_init(void __iomem *misc_base)
445{
446 struct clk *clk, *clk1;
447
448 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
449 32000);
450 clk_register_clkdev(clk, "osc_32k_clk", NULL);
451
452 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,

--- 560 unchanged lines hidden --- 		444{
445 struct clk *clk, *clk1;
446
447 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
448 32000);
449 clk_register_clkdev(clk, "osc_32k_clk", NULL);
450
451 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,

--- 560 unchanged lines hidden ---