| spear1340_clock.c (cd4b519aa5bdce92fcacc1d4bbe0fa16b4e16144) | spear1340_clock.c (ef0fd0a207c00b09449f33724322ba762d822d97) |
|---|---|
| 1/* 2 * arch/arm/mach-spear13xx/spear1340_clock.c 3 * 4 * SPEAr1340 machine clock framework source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <viresh.linux@gmail.com> 8 * --- 176 unchanged lines hidden (view full) --- 185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 186}; 187 188/* 189 * All below entries generate 166 MHz for 190 * different values of vco1div2 191 */ 192static struct frac_rate_tbl amba_synth_rtbl[] = { | 1/* 2 * arch/arm/mach-spear13xx/spear1340_clock.c 3 * 4 * SPEAr1340 machine clock framework source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <viresh.linux@gmail.com> 8 * --- 176 unchanged lines hidden (view full) --- 185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 186}; 187 188/* 189 * All below entries generate 166 MHz for 190 * different values of vco1div2 191 */ 192static struct frac_rate_tbl amba_synth_rtbl[] = { |
| 193 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */ |
|
| 193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */ 197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */ 198}; 199 200/* --- 14 unchanged lines hidden (view full) --- 215 * 400 400 200 0x02000 216 * -------------------------------------------------------------------- 217 * 500 200 100 0x05000 218 * 500 250 125 0x04000 219 * 500 332 166 0x03031 220 * 500 400 200 0x02800 221 * 500 500 250 0x02000 222 * -------------------------------------------------------------------- | 194 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 195 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 196 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 197 {.div = 0x03031}, /* for vco1div2 = 250 MHz */ 198 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */ 199}; 200 201/* --- 14 unchanged lines hidden (view full) --- 216 * 400 400 200 0x02000 217 * -------------------------------------------------------------------- 218 * 500 200 100 0x05000 219 * 500 250 125 0x04000 220 * 500 332 166 0x03031 221 * 500 400 200 0x02800 222 * 500 500 250 0x02000 223 * -------------------------------------------------------------------- |
| 224 * 600 200 100 0x06000 225 * 600 250 125 0x04CCE 226 * 600 332 166 0x039D5 227 * 600 400 200 0x03000 228 * 600 500 250 0x02666 229 * -------------------------------------------------------------------- |
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| 223 * 664 200 100 0x06a38 224 * 664 250 125 0x054FD 225 * 664 332 166 0x04000 226 * 664 400 200 0x0351E 227 * 664 500 250 0x02A7E 228 * -------------------------------------------------------------------- 229 * 800 200 100 0x08000 230 * 800 250 125 0x06666 231 * 800 332 166 0x04D18 232 * 800 400 200 0x04000 233 * 800 500 250 0x03333 234 * -------------------------------------------------------------------- 235 * sys rate configuration table is in descending order of divisor. 236 */ 237static struct frac_rate_tbl sys_synth_rtbl[] = { 238 {.div = 0x08000}, 239 {.div = 0x06a38}, 240 {.div = 0x06666}, | 230 * 664 200 100 0x06a38 231 * 664 250 125 0x054FD 232 * 664 332 166 0x04000 233 * 664 400 200 0x0351E 234 * 664 500 250 0x02A7E 235 * -------------------------------------------------------------------- 236 * 800 200 100 0x08000 237 * 800 250 125 0x06666 238 * 800 332 166 0x04D18 239 * 800 400 200 0x04000 240 * 800 500 250 0x03333 241 * -------------------------------------------------------------------- 242 * sys rate configuration table is in descending order of divisor. 243 */ 244static struct frac_rate_tbl sys_synth_rtbl[] = { 245 {.div = 0x08000}, 246 {.div = 0x06a38}, 247 {.div = 0x06666}, |
| 248 {.div = 0x06000}, |
|
| 241 {.div = 0x054FD}, 242 {.div = 0x05000}, 243 {.div = 0x04D18}, | 249 {.div = 0x054FD}, 250 {.div = 0x05000}, 251 {.div = 0x04D18}, |
| 252 {.div = 0x04CCE}, |
|
| 244 {.div = 0x04000}, | 253 {.div = 0x04000}, |
| 254 {.div = 0x039D5}, |
|
| 245 {.div = 0x0351E}, 246 {.div = 0x03333}, 247 {.div = 0x03031}, | 255 {.div = 0x0351E}, 256 {.div = 0x03333}, 257 {.div = 0x03031}, |
| 258 {.div = 0x03000}, |
|
| 248 {.div = 0x02A7E}, 249 {.div = 0x02800}, 250 {.div = 0x0268D}, | 259 {.div = 0x02A7E}, 260 {.div = 0x02800}, 261 {.div = 0x0268D}, |
| 262 {.div = 0x02666}, |
|
| 251 {.div = 0x02000}, 252}; 253 254/* aux rate configuration table, in ascending order of rates */ 255static struct aux_rate_tbl aux_rtbl[] = { | 263 {.div = 0x02000}, 264}; 265 266/* aux rate configuration table, in ascending order of rates */ 267static struct aux_rate_tbl aux_rtbl[] = { |
| 256 /* For VCO1div2 = 500 MHz */ 257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ | 268 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */ 269 {.xscale = 5, .yscale = 122, .eq = 0}, 270 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */ 271 {.xscale = 10, .yscale = 204, .eq = 0}, 272 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */ 273 {.xscale = 4, .yscale = 25, .eq = 0}, 274 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */ 275 {.xscale = 4, .yscale = 21, .eq = 0}, 276 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */ 277 {.xscale = 5, .yscale = 18, .eq = 0}, 278 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */ 279 {.xscale = 2, .yscale = 6, .eq = 0}, 280 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */ 281 {.xscale = 5, .yscale = 12, .eq = 0}, 282 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */ 283 {.xscale = 2, .yscale = 4, .eq = 0}, 284 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */ 285 {.xscale = 5, .yscale = 18, .eq = 1}, 286 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */ 287 {.xscale = 1, .yscale = 3, .eq = 1}, 288 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */ 289 {.xscale = 5, .yscale = 12, .eq = 1}, 290 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */ 291 {.xscale = 1, .yscale = 2, .eq = 1}, |
| 263}; 264 265/* gmac rate configuration table, in ascending order of rates */ 266static struct aux_rate_tbl gmac_rtbl[] = { 267 /* For gmac phy input clk */ 268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 272}; 273 274/* clcd rate configuration table, in ascending order of rates */ 275static struct frac_rate_tbl clcd_rtbl[] = { | 292}; 293 294/* gmac rate configuration table, in ascending order of rates */ 295static struct aux_rate_tbl gmac_rtbl[] = { 296 /* For gmac phy input clk */ 297 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 298 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 299 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 300 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 301}; 302 303/* clcd rate configuration table, in ascending order of rates */ 304static struct frac_rate_tbl clcd_rtbl[] = { |
| 305 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/ 306 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/ |
|
| 276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ | 307 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 308 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 309 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 310 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ |
| 311 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */ 312 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/ |
|
| 280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ | 313 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ |
| 314 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/ |
|
| 281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/ 282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ | 315 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/ 316 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 317 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 318 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ |
| 319 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/ |
|
| 285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ | 320 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ |
| 321 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/ |
|
| 286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/ 288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/ 289}; 290 291/* i2s prescaler1 masks */ 292static struct aux_clk_masks i2s_prs1_masks = { 293 .eq_sel_mask = AUX_EQ_SEL_MASK, --- 52 unchanged lines hidden (view full) --- 346 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 347 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 348 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 349 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 350}; 351 352/* General synth rate configuration table, in ascending order of rates */ 353static struct frac_rate_tbl gen_rtbl[] = { | 322 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 323 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/ 324 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/ 325}; 326 327/* i2s prescaler1 masks */ 328static struct aux_clk_masks i2s_prs1_masks = { 329 .eq_sel_mask = AUX_EQ_SEL_MASK, --- 52 unchanged lines hidden (view full) --- 382 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 383 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 384 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 385 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 386}; 387 388/* General synth rate configuration table, in ascending order of rates */ 389static struct frac_rate_tbl gen_rtbl[] = { |
| 354 /* For vco1div4 = 250 MHz */ 355 {.div = 0x1624E}, /* 22.5792 MHz */ 356 {.div = 0x14585}, /* 24.576 MHz */ 357 {.div = 0x14000}, /* 25 MHz */ 358 {.div = 0x0B127}, /* 45.1584 MHz */ 359 {.div = 0x0A000}, /* 50 MHz */ 360 {.div = 0x061A8}, /* 81.92 MHz */ 361 {.div = 0x05000}, /* 100 MHz */ 362 {.div = 0x02800}, /* 200 MHz */ 363 {.div = 0x02620}, /* 210 MHz */ 364 {.div = 0x02460}, /* 220 MHz */ 365 {.div = 0x022C0}, /* 230 MHz */ 366 {.div = 0x02160}, /* 240 MHz */ 367 {.div = 0x02000}, /* 250 MHz */ | 390 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/ 391 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/ 392 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/ 393 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/ 394 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/ 395 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/ 396 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/ 397 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/ 398 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/ 399 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/ 400 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/ 401 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/ 402 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/ 403 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/ 404 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/ 405 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/ 406 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/ 407 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/ 408 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/ 409 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/ 410 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/ 411 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/ 412 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/ 413 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/ 414 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/ |
| 368}; 369 370/* clock parents */ 371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 372static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 373 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", }; 374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; --- 593 unchanged lines hidden --- | 415}; 416 417/* clock parents */ 418static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 419static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 420 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", }; 421static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 422static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; --- 593 unchanged lines hidden --- |