spear1310_clock.c (463f9e209ca69d52344479544d1e52c02f2e6918) spear1310_clock.c (1249979242db10d2fe1793f26e7658d94b7bf6dc)
1/*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *

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478 clk_register_clkdev(clk, NULL, "spear_thermal");
479
480 /* clock derived from pll4 clk */
481 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
482 1);
483 clk_register_clkdev(clk, "ddr_clk", NULL);
484
485 /* clock derived from pll1 clk */
1/*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *

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478 clk_register_clkdev(clk, NULL, "spear_thermal");
479
480 /* clock derived from pll4 clk */
481 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
482 1);
483 clk_register_clkdev(clk, "ddr_clk", NULL);
484
485 /* clock derived from pll1 clk */
486 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
486 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
487 CLK_SET_RATE_PARENT, 1, 2);
487 clk_register_clkdev(clk, "cpu_clk", NULL);
488
489 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
490 2);
491 clk_register_clkdev(clk, NULL, "ec800620.wdt");
492
493 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
494 6);

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542 /* others */
543 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
544 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
545 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
546 clk_register_clkdev(clk, "uart_syn_clk", NULL);
547 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
548
549 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
488 clk_register_clkdev(clk, "cpu_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, NULL, "ec800620.wdt");
493
494 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
495 6);

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543 /* others */
544 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
545 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
546 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
547 clk_register_clkdev(clk, "uart_syn_clk", NULL);
548 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
549
550 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
550 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
551 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
552 &_lock);
551 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
552 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
553 SPEAR1310_UART_CLK_MASK, 0, &_lock);
553 clk_register_clkdev(clk, "uart0_mclk", NULL);
554
554 clk_register_clkdev(clk, "uart0_mclk", NULL);
555
555 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0,
556 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
557 &_lock);
556 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
557 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
558 SPEAR1310_UART_CLK_ENB, 0, &_lock);
558 clk_register_clkdev(clk, NULL, "e0000000.serial");
559
560 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
561 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
562 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
563 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
564 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
565
559 clk_register_clkdev(clk, NULL, "e0000000.serial");
560
561 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
562 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
563 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
564 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
565 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
566
566 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0,
567 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
568 &_lock);
567 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
568 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
569 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
569 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
570
571 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
572 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
573 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
574 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
575 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
576
570 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
571
572 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
573 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
574 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
576 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
577
577 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0,
578 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
579 &_lock);
578 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
579 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
580 SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, NULL, "b2800000.cf");
581 clk_register_clkdev(clk, NULL, "arasan_xd");
582
583 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
584 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
585 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
586 clk_register_clkdev(clk, "c3_syn_clk", NULL);
587 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
588
589 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
581 clk_register_clkdev(clk, NULL, "b2800000.cf");
582 clk_register_clkdev(clk, NULL, "arasan_xd");
583
584 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
585 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
586 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
587 clk_register_clkdev(clk, "c3_syn_clk", NULL);
588 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
589
590 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
590 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
591 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
592 &_lock);
591 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
592 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
593 SPEAR1310_C3_CLK_MASK, 0, &_lock);
593 clk_register_clkdev(clk, "c3_mclk", NULL);
594
595 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
596 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
597 &_lock);
598 clk_register_clkdev(clk, NULL, "c3");
599
600 /* gmac */

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625 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
626
627 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
628 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
629 ARRAY_SIZE(clcd_rtbl), &_lock);
630 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
631
632 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
594 clk_register_clkdev(clk, "c3_mclk", NULL);
595
596 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
597 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
598 &_lock);
599 clk_register_clkdev(clk, NULL, "c3");
600
601 /* gmac */

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626 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
627
628 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
629 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
630 ARRAY_SIZE(clcd_rtbl), &_lock);
631 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
632
633 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
633 ARRAY_SIZE(clcd_pixel_parents), 0,
634 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
634 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
635 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
636 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
637
638 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
639 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
640 &_lock);
641 clk_register_clkdev(clk, NULL, "e1000000.clcd");

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648 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
649
650 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
651 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
652 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
653 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
654
655 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
635 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
636 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
637 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
638
639 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
640 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
641 &_lock);
642 clk_register_clkdev(clk, NULL, "e1000000.clcd");

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649 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
650
651 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
652 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
653 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
654 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
655
656 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
656 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
657 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
658 &_lock);
659 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
657 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
658 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
659 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
660 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
660
661 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
662 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
663 0, &_lock);
664 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
665
666 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
667 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,

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748 clk_register_clkdev(clk, "sysram1_clk", NULL);
749
750 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
751 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
752 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
753 clk_register_clkdev(clk, "adc_syn_clk", NULL);
754 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
755
661
662 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
663 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
664 0, &_lock);
665 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
666
667 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
668 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,

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749 clk_register_clkdev(clk, "sysram1_clk", NULL);
750
751 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
752 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
753 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
754 clk_register_clkdev(clk, "adc_syn_clk", NULL);
755 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
756
756 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
758 &_lock);
757 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
758 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
759 SPEAR1310_ADC_CLK_ENB, 0, &_lock);
759 clk_register_clkdev(clk, NULL, "e0080000.adc");
760
761 /* clock derived from apb clk */
762 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
763 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "e0100000.spi");
766

--- 340 unchanged lines hidden --- 		760 clk_register_clkdev(clk, NULL, "e0080000.adc");
761
762 /* clock derived from apb clk */
763 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
764 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
765 &_lock);
766 clk_register_clkdev(clk, NULL, "e0100000.spi");
767

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