clk-s10.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) clk-s10.c (ba7e258425acd8587b62196e3f00f62c0f7625d0)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7#include <linux/of_device.h>
8#include <linux/of_address.h>

--- 260 unchanged lines hidden (view full) ---

269 10, 0, 0, 0, 0, 0, 4},
270 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
271 10, 0, 0, 0, 0, 0, 4},
272};
273
274static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
275 int nums, struct stratix10_clock_data *data)
276{
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017, Intel Corporation
4 */
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7#include <linux/of_device.h>
8#include <linux/of_address.h>

--- 260 unchanged lines hidden (view full) ---

269 10, 0, 0, 0, 0, 0, 4},
270 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
271 10, 0, 0, 0, 0, 0, 4},
272};
273
274static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
275 int nums, struct stratix10_clock_data *data)
276{
277 struct clk *clk;
277 struct clk_hw *hw_clk;
278 void __iomem *base = data->base;
279 int i;
280
281 for (i = 0; i < nums; i++) {
278 void __iomem *base = data->base;
279 int i;
280
281 for (i = 0; i < nums; i++) {
282 clk = s10_register_periph(&clks[i], base);
283 if (IS_ERR(clk)) {
282 hw_clk = s10_register_periph(&clks[i], base);
283 if (IS_ERR(hw_clk)) {
284 pr_err("%s: failed to register clock %s\n",
285 __func__, clks[i].name);
286 continue;
287 }
284 pr_err("%s: failed to register clock %s\n",
285 __func__, clks[i].name);
286 continue;
287 }
288 data->clk_data.clks[clks[i].id] = clk;
288 data->clk_data.hws[clks[i].id] = hw_clk;
289 }
290 return 0;
291}
292
293static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
294 int nums, struct stratix10_clock_data *data)
295{
289 }
290 return 0;
291}
292
293static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
294 int nums, struct stratix10_clock_data *data)
295{
296 struct clk *clk;
296 struct clk_hw *hw_clk;
297 void __iomem *base = data->base;
298 int i;
299
300 for (i = 0; i < nums; i++) {
297 void __iomem *base = data->base;
298 int i;
299
300 for (i = 0; i < nums; i++) {
301 clk = s10_register_cnt_periph(&clks[i], base);
302 if (IS_ERR(clk)) {
301 hw_clk = s10_register_cnt_periph(&clks[i], base);
302 if (IS_ERR(hw_clk)) {
303 pr_err("%s: failed to register clock %s\n",
304 __func__, clks[i].name);
305 continue;
306 }
303 pr_err("%s: failed to register clock %s\n",
304 __func__, clks[i].name);
305 continue;
306 }
307 data->clk_data.clks[clks[i].id] = clk;
307 data->clk_data.hws[clks[i].id] = hw_clk;
308 }
309
310 return 0;
311}
312
313static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
314 int nums, struct stratix10_clock_data *data)
315{
308 }
309
310 return 0;
311}
312
313static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
314 int nums, struct stratix10_clock_data *data)
315{
316 struct clk *clk;
316 struct clk_hw *hw_clk;
317 void __iomem *base = data->base;
318 int i;
319
320 for (i = 0; i < nums; i++) {
317 void __iomem *base = data->base;
318 int i;
319
320 for (i = 0; i < nums; i++) {
321 clk = s10_register_gate(&clks[i], base);
322 if (IS_ERR(clk)) {
321 hw_clk = s10_register_gate(&clks[i], base);
322 if (IS_ERR(hw_clk)) {
323 pr_err("%s: failed to register clock %s\n",
324 __func__, clks[i].name);
325 continue;
326 }
323 pr_err("%s: failed to register clock %s\n",
324 __func__, clks[i].name);
325 continue;
326 }
327 data->clk_data.clks[clks[i].id] = clk;
327 data->clk_data.hws[clks[i].id] = hw_clk;
328 }
329
330 return 0;
331}
332
333static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
334 int nums, struct stratix10_clock_data *data)
335{
328 }
329
330 return 0;
331}
332
333static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
334 int nums, struct stratix10_clock_data *data)
335{
336 struct clk *clk;
336 struct clk_hw *hw_clk;
337 void __iomem *base = data->base;
338 int i;
339
340 for (i = 0; i < nums; i++) {
337 void __iomem *base = data->base;
338 int i;
339
340 for (i = 0; i < nums; i++) {
341 clk = s10_register_pll(&clks[i], base);
342 if (IS_ERR(clk)) {
341 hw_clk = s10_register_pll(&clks[i], base);
342 if (IS_ERR(hw_clk)) {
343 pr_err("%s: failed to register clock %s\n",
344 __func__, clks[i].name);
345 continue;
346 }
343 pr_err("%s: failed to register clock %s\n",
344 __func__, clks[i].name);
345 continue;
346 }
347 data->clk_data.clks[clks[i].id] = clk;
347 data->clk_data.hws[clks[i].id] = hw_clk;
348 }
349
350 return 0;
351}
352
348 }
349
350 return 0;
351}
352
353static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
354 int nr_clks)
353static int s10_clkmgr_init(struct platform_device *pdev)
355{
356 struct device_node *np = pdev->dev.of_node;
357 struct device *dev = &pdev->dev;
358 struct stratix10_clock_data *clk_data;
354{
355 struct device_node *np = pdev->dev.of_node;
356 struct device *dev = &pdev->dev;
357 struct stratix10_clock_data *clk_data;
359 struct clk **clk_table;
360 struct resource *res;
361 void __iomem *base;
358 struct resource *res;
359 void __iomem *base;
360 int i, num_clks;
362
363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 base = devm_ioremap_resource(dev, res);
365 if (IS_ERR(base)) {
366 pr_err("%s: failed to map clock registers\n", __func__);
361
362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 base = devm_ioremap_resource(dev, res);
364 if (IS_ERR(base)) {
365 pr_err("%s: failed to map clock registers\n", __func__);
367 return ERR_CAST(base);
366 return PTR_ERR(base);
368 }
369
367 }
368
370 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
369 num_clks = STRATIX10_NUM_CLKS;
370 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
371 num_clks), GFP_KERNEL);
371 if (!clk_data)
372 if (!clk_data)
372 return ERR_PTR(-ENOMEM);
373 return -ENOMEM;
373
374
375 for (i = 0; i < num_clks; i++)
376 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
377
374 clk_data->base = base;
378 clk_data->base = base;
375 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
376 if (!clk_table)
377 return ERR_PTR(-ENOMEM);
379 clk_data->clk_data.num = num_clks;
378
380
379 clk_data->clk_data.clks = clk_table;
380 clk_data->clk_data.clk_num = nr_clks;
381 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
382 return clk_data;
383}
384
385static int s10_clkmgr_init(struct platform_device *pdev)
386{
387 struct stratix10_clock_data *clk_data;
388
389 clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
390 if (IS_ERR(clk_data))
391 return PTR_ERR(clk_data);
392
393 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
394
395 s10_clk_register_c_perip(s10_main_perip_c_clks,
396 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
397
398 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
399 ARRAY_SIZE(s10_main_perip_cnt_clks),
400 clk_data);
401
402 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
403 clk_data);
381 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
382
383 s10_clk_register_c_perip(s10_main_perip_c_clks,
384 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
385
386 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
387 ARRAY_SIZE(s10_main_perip_cnt_clks),
388 clk_data);
389
390 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
391 clk_data);
392
393 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
404 return 0;
405}
406
407static int s10_clkmgr_probe(struct platform_device *pdev)
408{
409 return s10_clkmgr_init(pdev);
410}
411

--- 20 unchanged lines hidden --- 		394 return 0;
395}
396
397static int s10_clkmgr_probe(struct platform_device *pdev)
398{
399 return s10_clkmgr_init(pdev);
400}
401

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