| sifive-prci.h (efc91ae43c8d4bbf64e4b9a28113b24a74ffd58d) | sifive-prci.h (263ac3908516abb0392747bbf595af2b13df5fa2) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2018-2019 SiFive, Inc. 4 * Wesley Terpstra 5 * Paul Walmsley 6 * Zong Li 7 */ 8 --- 45 unchanged lines hidden (view full) --- 54#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) 55#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 56#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) 57#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 58#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) 59 60/* DDRPLLCFG1 */ 61#define PRCI_DDRPLLCFG1_OFFSET 0x10 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2018-2019 SiFive, Inc. 4 * Wesley Terpstra 5 * Paul Walmsley 6 * Zong Li 7 */ 8 --- 45 unchanged lines hidden (view full) --- 54#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) 55#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 56#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) 57#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 58#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) 59 60/* DDRPLLCFG1 */ 61#define PRCI_DDRPLLCFG1_OFFSET 0x10 |
| 62#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 | 62#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 |
| 63#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) 64 65/* GEMGXLPLLCFG0 */ 66#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c 67#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 68#define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) 69#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 70#define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) --- 5 unchanged lines hidden (view full) --- 76#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) 77#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 78#define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) 79#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 80#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) 81 82/* GEMGXLPLLCFG1 */ 83#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 | 63#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) 64 65/* GEMGXLPLLCFG0 */ 66#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c 67#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 68#define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) 69#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 70#define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) --- 5 unchanged lines hidden (view full) --- 76#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) 77#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 78#define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) 79#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 80#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) 81 82/* GEMGXLPLLCFG1 */ 83#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 |
| 84#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 | 84#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 |
| 85#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) 86 87/* CORECLKSEL */ 88#define PRCI_CORECLKSEL_OFFSET 0x24 89#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 90#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ 91 (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) 92 --- 197 unchanged lines hidden --- | 85#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) 86 87/* CORECLKSEL */ 88#define PRCI_CORECLKSEL_OFFSET 0x24 89#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 90#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ 91 (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) 92 --- 197 unchanged lines hidden --- |