sifive-prci.h (c816e1ddf2b60b31d121118488c5a854d9a2fad9) sifive-prci.h (efc91ae43c8d4bbf64e4b9a28113b24a74ffd58d)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8

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112 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
113
114/* CLKMUXSTATUSREG */
115#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
116#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
117#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
118 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
119
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8

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112 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
113
114/* CLKMUXSTATUSREG */
115#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
116#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
117#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
118 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
119
120/* CLTXPLLCFG0 */
121#define PRCI_CLTXPLLCFG0_OFFSET 0x30
122#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0
123#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT)
124#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6
125#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT)
126#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15
127#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT)
128#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18
129#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT)
130#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24
131#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT)
132#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25
133#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT)
134#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31
135#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT)
136
137/* CLTXPLLCFG1 */
138#define PRCI_CLTXPLLCFG1_OFFSET 0x34
139#define PRCI_CLTXPLLCFG1_CKE_SHIFT 31
140#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT)
141
142/* DVFSCOREPLLCFG0 */
143#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38
144
145/* DVFSCOREPLLCFG1 */
146#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c
147#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 31
148#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT)
149
150/* COREPLLSEL */
151#define PRCI_COREPLLSEL_OFFSET 0x40
152#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0
153#define PRCI_COREPLLSEL_COREPLLSEL_MASK \
154 (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT)
155
156/* HFPCLKPLLCFG0 */
157#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50
158#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0
159#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \
160 (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT)
161#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6
162#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \
163 (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT)
164#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15
165#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \
166 (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT)
167#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18
168#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \
169 (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT)
170#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24
171#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \
172 (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT)
173#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25
174#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \
175 (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT)
176#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31
177#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \
178 (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT)
179
180/* HFPCLKPLLCFG1 */
181#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54
182#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 31
183#define PRCI_HFPCLKPLLCFG1_CKE_MASK \
184 (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT)
185
186/* HFPCLKPLLSEL */
187#define PRCI_HFPCLKPLLSEL_OFFSET 0x58
188#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0
189#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \
190 (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT)
191
192/* HFPCLKPLLDIV */
193#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c
194
195/* PRCIPLL */
196#define PRCI_PRCIPLL_OFFSET 0xe0
197
198/* PROCMONCFG */
199#define PRCI_PROCMONCFG_OFFSET 0xf0
200
120/*
121 * Private structures
122 */
123
124/**
125 * struct __prci_data - per-device-instance data
126 * @va: base virtual address of the PRCI IP block
127 * @hw_clks: encapsulates struct clk_hw records

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182struct prci_clk_desc {
183 struct __prci_clock *clks;
184 size_t num_clks;
185};
186
187/* Core clock mux control */
188void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd);
189void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd);
201/*
202 * Private structures
203 */
204
205/**
206 * struct __prci_data - per-device-instance data
207 * @va: base virtual address of the PRCI IP block
208 * @hw_clks: encapsulates struct clk_hw records

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263struct prci_clk_desc {
264 struct __prci_clock *clks;
265 size_t num_clks;
266};
267
268/* Core clock mux control */
269void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd);
270void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd);
271void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd);
272void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd);
273void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd);
274void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
275void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
190
191/* Linux clock framework integration */
192long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
193 unsigned long *parent_rate);
194int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
195 unsigned long parent_rate);
196unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
197 unsigned long parent_rate);
198unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
199 unsigned long parent_rate);
276
277/* Linux clock framework integration */
278long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
279 unsigned long *parent_rate);
280int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
281 unsigned long parent_rate);
282unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
283 unsigned long parent_rate);
284unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
285 unsigned long parent_rate);
286unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
287 unsigned long parent_rate);
200
201#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
288
289#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */