sifive-prci.h (c61287bf17836b67e0b649343778bb4a659bd70d) sifive-prci.h (e4d368e0b632717e57d064ade6afdcf535e58068)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8
9#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H
10#define __SIFIVE_CLK_SIFIVE_PRCI_H
11
12#include <linux/clk/analogbits-wrpll-cln28hpc.h>
13#include <linux/clk-provider.h>
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8
9#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H
10#define __SIFIVE_CLK_SIFIVE_PRCI_H
11
12#include <linux/clk/analogbits-wrpll-cln28hpc.h>
13#include <linux/clk-provider.h>
14#include <linux/reset/reset-simple.h>
14#include <linux/platform_device.h>
15
16/*
17 * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
18 * hfclk and rtcclk
19 */
20#define EXPECTED_CLK_PARENT_COUNT 2
21

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116 (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
117#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
118#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
119 (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
120#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6
121#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
122 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
123
15#include <linux/platform_device.h>
16
17/*
18 * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
19 * hfclk and rtcclk
20 */
21#define EXPECTED_CLK_PARENT_COUNT 2
22

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117 (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
118#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
119#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
120 (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
121#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6
122#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
123 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
124
125#define PRCI_RST_NR 7
126
124/* CLKMUXSTATUSREG */
125#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
126#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
127#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
128 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
129
130/* CLTXPLLCFG0 */
131#define PRCI_CLTXPLLCFG0_OFFSET 0x30

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216 * struct __prci_data - per-device-instance data
217 * @va: base virtual address of the PRCI IP block
218 * @hw_clks: encapsulates struct clk_hw records
219 *
220 * PRCI per-device instance data
221 */
222struct __prci_data {
223 void __iomem *va;
127/* CLKMUXSTATUSREG */
128#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
129#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
130#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
131 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
132
133/* CLTXPLLCFG0 */
134#define PRCI_CLTXPLLCFG0_OFFSET 0x30

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219 * struct __prci_data - per-device-instance data
220 * @va: base virtual address of the PRCI IP block
221 * @hw_clks: encapsulates struct clk_hw records
222 *
223 * PRCI per-device instance data
224 */
225struct __prci_data {
226 void __iomem *va;
227 struct reset_simple_data reset;
224 struct clk_hw_onecell_data hw_clks;
225};
226
227/**
228 * struct __prci_wrpll_data - WRPLL configuration and integration data
229 * @c: WRPLL current configuration record
230 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
231 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)

--- 77 unchanged lines hidden --- 		228 struct clk_hw_onecell_data hw_clks;
229};
230
231/**
232 * struct __prci_wrpll_data - WRPLL configuration and integration data
233 * @c: WRPLL current configuration record
234 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
235 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)

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