sifive-prci.h (263ac3908516abb0392747bbf595af2b13df5fa2) sifive-prci.h (732374a0b440d9a79c8412f318a25cd37ba6f4e2)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8

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35#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
36#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
37#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
38#define PRCI_COREPLLCFG0_FSE_SHIFT 25
39#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
40#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
41#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
42
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra
5 * Paul Walmsley
6 * Zong Li
7 */
8

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35#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
36#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
37#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
38#define PRCI_COREPLLCFG0_FSE_SHIFT 25
39#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
40#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
41#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
42
43/* COREPLLCFG1 */
44#define PRCI_COREPLLCFG1_OFFSET 0x8
45#define PRCI_COREPLLCFG1_CKE_SHIFT 31
46#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
47
43/* DDRPLLCFG0 */
44#define PRCI_DDRPLLCFG0_OFFSET 0xc
45#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
46#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
47#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
48#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
49#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
50#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)

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215};
216
217/**
218 * struct __prci_wrpll_data - WRPLL configuration and integration data
219 * @c: WRPLL current configuration record
220 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
221 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
222 * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
48/* DDRPLLCFG0 */
49#define PRCI_DDRPLLCFG0_OFFSET 0xc
50#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
51#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
52#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
53#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
54#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
55#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)

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220};
221
222/**
223 * struct __prci_wrpll_data - WRPLL configuration and integration data
224 * @c: WRPLL current configuration record
225 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
226 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
227 * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
228 * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
223 *
224 * @enable_bypass and @disable_bypass are used for WRPLL instances
225 * that contain a separate external glitchless clock mux downstream
226 * from the PLL. The WRPLL internal bypass mux is not glitchless.
227 */
228struct __prci_wrpll_data {
229 struct wrpll_cfg c;
230 void (*enable_bypass)(struct __prci_data *pd);
231 void (*disable_bypass)(struct __prci_data *pd);
232 u8 cfg0_offs;
229 *
230 * @enable_bypass and @disable_bypass are used for WRPLL instances
231 * that contain a separate external glitchless clock mux downstream
232 * from the PLL. The WRPLL internal bypass mux is not glitchless.
233 */
234struct __prci_wrpll_data {
235 struct wrpll_cfg c;
236 void (*enable_bypass)(struct __prci_data *pd);
237 void (*disable_bypass)(struct __prci_data *pd);
238 u8 cfg0_offs;
239 u8 cfg1_offs;
233};
234
235/**
236 * struct __prci_clock - describes a clock device managed by PRCI
237 * @name: user-readable clock name string - should match the manual
238 * @parent_name: parent name for this clock
239 * @ops: struct clk_ops for the Linux clock framework to use for control
240 * @hw: Linux-private clock data

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274void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
275void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
276
277/* Linux clock framework integration */
278long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
279 unsigned long *parent_rate);
280int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
281 unsigned long parent_rate);
240};
241
242/**
243 * struct __prci_clock - describes a clock device managed by PRCI
244 * @name: user-readable clock name string - should match the manual
245 * @parent_name: parent name for this clock
246 * @ops: struct clk_ops for the Linux clock framework to use for control
247 * @hw: Linux-private clock data

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281void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
282void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
283
284/* Linux clock framework integration */
285long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
286 unsigned long *parent_rate);
287int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
288 unsigned long parent_rate);
289int sifive_clk_is_enabled(struct clk_hw *hw);
290int sifive_prci_clock_enable(struct clk_hw *hw);
291void sifive_prci_clock_disable(struct clk_hw *hw);
282unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
283 unsigned long parent_rate);
284unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
285 unsigned long parent_rate);
286unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
287 unsigned long parent_rate);
288
289#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
292unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
293 unsigned long parent_rate);
294unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
295 unsigned long parent_rate);
296unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
297 unsigned long parent_rate);
298
299#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */