| clk-exynos5433.c (0cce284537fb42d9c28b9b31038ffc9b464555f5) | clk-exynos5433.c (5ccb58968bf7f46dbd128df88f71838a5a9750b8) |
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| 1/* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 2545 unchanged lines hidden (view full) --- 2554 1, 2, 0), 2555}; 2556 2557static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2558 /* PHY clocks from MIPI_DPHY1 */ 2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2561 /* PHY clocks from MIPI_DPHY0 */ | 1/* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 2545 unchanged lines hidden (view full) --- 2554 1, 2, 0), 2555}; 2556 2557static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2558 /* PHY clocks from MIPI_DPHY1 */ 2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2561 /* PHY clocks from MIPI_DPHY0 */ |
| 2562 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), 2563 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), | 2562 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", 2563 NULL, 0, 188000000), 2564 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", 2565 NULL, 0, 100000000), |
| 2564 /* PHY clocks from HDMI_PHY */ 2565 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2566 NULL, 0, 300000000), 2567 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2568 NULL, 0, 166000000), 2569}; 2570 2571static const struct samsung_mux_clock disp_mux_clks[] __initconst = { --- 2838 unchanged lines hidden --- | 2566 /* PHY clocks from HDMI_PHY */ 2567 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2568 NULL, 0, 300000000), 2569 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2570 NULL, 0, 166000000), 2571}; 2572 2573static const struct samsung_mux_clock disp_mux_clks[] __initconst = { --- 2838 unchanged lines hidden --- |