clk-exynos5250.c (1d5013f1b64dbd692975be5db0e42bac291c6de9) clk-exynos5250.c (edcefb96fb07f6742fd47ac60915e76c1b77768e)
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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13#include <dt-bindings/clock/exynos5250.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#include "clk.h"
20#include "clk-cpu.h"
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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13#include <dt-bindings/clock/exynos5250.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#include "clk.h"
20#include "clk-cpu.h"
21#include "clk-exynos5-subcmu.h"
21
22#define APLL_LOCK 0x0
23#define APLL_CON0 0x100
24#define SRC_CPU 0x200
25#define DIV_CPU0 0x500
26#define PWR_CTRL1 0x1020
27#define PWR_CTRL2 0x1024
28#define MPLL_LOCK 0x4000

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566 GATE_IP_GSCL, 7, 0, 0),
567 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
568 GATE_IP_GSCL, 8, 0, 0),
569 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
570 GATE_IP_GSCL, 9, 0, 0),
571 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
572 GATE_IP_GSCL, 10, 0, 0),
573
22
23#define APLL_LOCK 0x0
24#define APLL_CON0 0x100
25#define SRC_CPU 0x200
26#define DIV_CPU0 0x500
27#define PWR_CTRL1 0x1020
28#define PWR_CTRL2 0x1024
29#define MPLL_LOCK 0x4000

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567 GATE_IP_GSCL, 7, 0, 0),
568 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
569 GATE_IP_GSCL, 8, 0, 0),
570 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
571 GATE_IP_GSCL, 9, 0, 0),
572 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
573 GATE_IP_GSCL, 10, 0, 0),
574
574 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
575 0),
576 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
577 0),
578 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
579 0),
580 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
581 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
582 0),
583 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
584 0),
585
586 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
587 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
588 0),
589 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
590 0),
591 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
592 CLK_SET_RATE_PARENT, 0),

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666 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
667 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
668 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
669 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
670 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
671 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
672 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
673 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
575
576 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
577 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
578 0),
579 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
580 0),
581 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
582 CLK_SET_RATE_PARENT, 0),

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656 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
657 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
658 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
659 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
660 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
661 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
662 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
663 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
674 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
675 GATE_IP_DISP1, 9, 0, 0),
676 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
677 GATE_IP_DISP1, 8, 0, 0),
678 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
679 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
680 GATE_IP_ISP0, 8, 0, 0),
681 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
682 GATE_IP_ISP0, 9, 0, 0),
683 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
684 GATE_IP_ISP0, 10, 0, 0),
685 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",

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693 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
694 GATE_IP_ISP1, 5, 0, 0),
695 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
696 GATE_IP_ISP1, 6, 0, 0),
697 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
698 GATE_IP_ISP1, 7, 0, 0),
699};
700
664 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
665 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
666 GATE_IP_ISP0, 8, 0, 0),
667 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
668 GATE_IP_ISP0, 9, 0, 0),
669 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
670 GATE_IP_ISP0, 10, 0, 0),
671 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",

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679 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
680 GATE_IP_ISP1, 5, 0, 0),
681 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
682 GATE_IP_ISP1, 6, 0, 0),
683 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
684 GATE_IP_ISP1, 7, 0, 0),
685};
686
687static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
688 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
689 0),
690 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
691 0),
692 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
693 0),
694 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
695 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
696 0),
697 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
698 0),
699 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
700 GATE_IP_DISP1, 9, 0, 0),
701 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
702 GATE_IP_DISP1, 8, 0, 0),
703};
704
705static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
706 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
707 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */
708 { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */
709};
710
711static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
712 .gate_clks = exynos5250_disp_gate_clks,
713 .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks),
714 .suspend_regs = exynos5250_disp_suspend_regs,
715 .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
716 .pd_name = "DISP1",
717};
718
701static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
702 /* sorted in descending order */
703 /* PLL_36XX_RATE(rate, m, p, s, k) */
704 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
705 /* Not in UM, but need for eDP on snow */
706 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
707 { },
708};

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854 * ratios.
855 */
856 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
857 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
858 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
859 __raw_writel(tmp, reg_base + PWR_CTRL2);
860
861 exynos5250_clk_sleep_init();
719static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
720 /* sorted in descending order */
721 /* PLL_36XX_RATE(rate, m, p, s, k) */
722 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
723 /* Not in UM, but need for eDP on snow */
724 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
725 { },
726};

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872 * ratios.
873 */
874 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
875 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
876 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
877 __raw_writel(tmp, reg_base + PWR_CTRL2);
878
879 exynos5250_clk_sleep_init();
880 exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
862
863 samsung_clk_of_add_provider(np, ctx);
864
865 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
866 _get_rate("div_arm2"));
867}
881
882 samsung_clk_of_add_provider(np, ctx);
883
884 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
885 _get_rate("div_arm2"));
886}
868CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
887CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);