clk.h (b70366e5d31788650b2a5cec5cd13ea80ac7e44a) clk.h (7e2a9035c1dbc4632f1897a8fe580fc90f33c013)
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

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29#include <linux/io.h>
30#include <linux/clk-provider.h>
31
32struct clk;
33
34#define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
36
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

--- 20 unchanged lines hidden (view full) ---

29#include <linux/io.h>
30#include <linux/clk-provider.h>
31
32struct clk;
33
34#define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
36
37/* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
38#define RK1108_PLL_CON(x) ((x) * 0x4)
39#define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
40#define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
41#define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
42#define RK1108_GLB_SRST_FST 0x1c0
43#define RK1108_GLB_SRST_SND 0x1c4
44#define RK1108_MISC_CON 0x1cc
45#define RK1108_SDMMC_CON0 0x1d8
46#define RK1108_SDMMC_CON1 0x1dc
47#define RK1108_SDIO_CON0 0x1e0
48#define RK1108_SDIO_CON1 0x1e4
49#define RK1108_EMMC_CON0 0x1e8
50#define RK1108_EMMC_CON1 0x1ec
37/* register positions shared by RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
38#define RV1108_PLL_CON(x) ((x) * 0x4)
39#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
40#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
41#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
42#define RV1108_GLB_SRST_FST 0x1c0
43#define RV1108_GLB_SRST_SND 0x1c4
44#define RV1108_MISC_CON 0x1cc
45#define RV1108_SDMMC_CON0 0x1d8
46#define RV1108_SDMMC_CON1 0x1dc
47#define RV1108_SDIO_CON0 0x1e0
48#define RV1108_SDIO_CON1 0x1e4
49#define RV1108_EMMC_CON0 0x1e8
50#define RV1108_EMMC_CON1 0x1ec
51
52#define RK2928_PLL_CON(x) ((x) * 0x4)
53#define RK2928_MODE_CON 0x40
54#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
55#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
56#define RK2928_GLB_SRST_FST 0x100
57#define RK2928_GLB_SRST_SND 0x104
58#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)

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52#define RK2928_PLL_CON(x) ((x) * 0x4)
53#define RK2928_MODE_CON 0x40
54#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
55#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
56#define RK2928_GLB_SRST_FST 0x100
57#define RK2928_GLB_SRST_SND 0x104
58#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)

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