clk.h (a402eae64d0ad12b1c4a411f250d6c161e67f623) clk.h (fe3511ad8a1cf63721f5f3e64996e16006e1d7d2)
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

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86#define RK3288_SDMMC_CON1 0x204
87#define RK3288_SDIO0_CON0 0x208
88#define RK3288_SDIO0_CON1 0x20c
89#define RK3288_SDIO1_CON0 0x210
90#define RK3288_SDIO1_CON1 0x214
91#define RK3288_EMMC_CON0 0x218
92#define RK3288_EMMC_CON1 0x21c
93
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

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86#define RK3288_SDMMC_CON1 0x204
87#define RK3288_SDIO0_CON0 0x208
88#define RK3288_SDIO0_CON1 0x20c
89#define RK3288_SDIO1_CON0 0x210
90#define RK3288_SDIO1_CON1 0x214
91#define RK3288_EMMC_CON0 0x218
92#define RK3288_EMMC_CON1 0x21c
93
94#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
95#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
96#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
97#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
98#define RK3328_GLB_SRST_FST 0x9c
99#define RK3328_GLB_SRST_SND 0x98
100#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
101#define RK3328_MODE_CON 0x80
102#define RK3328_MISC_CON 0x84
103#define RK3328_SDMMC_CON0 0x380
104#define RK3328_SDMMC_CON1 0x384
105#define RK3328_SDIO_CON0 0x388
106#define RK3328_SDIO_CON1 0x38c
107#define RK3328_EMMC_CON0 0x390
108#define RK3328_EMMC_CON1 0x394
109#define RK3328_SDMMC_EXT_CON0 0x398
110#define RK3328_SDMMC_EXT_CON1 0x39C
111
94#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
95#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
96#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
97#define RK3368_GLB_SRST_FST 0x280
98#define RK3368_GLB_SRST_SND 0x284
99#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
100#define RK3368_MISC_CON 0x380
101#define RK3368_SDMMC_CON0 0x400

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125#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
126#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
127#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
128#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
129
130enum rockchip_pll_type {
131 pll_rk3036,
132 pll_rk3066,
112#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
113#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
114#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
115#define RK3368_GLB_SRST_FST 0x280
116#define RK3368_GLB_SRST_SND 0x284
117#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
118#define RK3368_MISC_CON 0x380
119#define RK3368_SDMMC_CON0 0x400

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143#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
144#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
145#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
146#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
147
148enum rockchip_pll_type {
149 pll_rk3036,
150 pll_rk3066,
151 pll_rk3328,
133 pll_rk3399,
134};
135
136#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
137 _postdiv2, _dsmpd, _frac) \
138{ \
139 .rate = _rate##U, \
140 .fbdiv = _fbdiv, \

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312
313#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
314
315struct clk *rockchip_clk_register_inverter(const char *name,
316 const char *const *parent_names, u8 num_parents,
317 void __iomem *reg, int shift, int flags,
318 spinlock_t *lock);
319
152 pll_rk3399,
153};
154
155#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
156 _postdiv2, _dsmpd, _frac) \
157{ \
158 .rate = _rate##U, \
159 .fbdiv = _fbdiv, \

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331
332#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
333
334struct clk *rockchip_clk_register_inverter(const char *name,
335 const char *const *parent_names, u8 num_parents,
336 void __iomem *reg, int shift, int flags,
337 spinlock_t *lock);
338
339struct clk *rockchip_clk_register_muxgrf(const char *name,
340 const char *const *parent_names, u8 num_parents,
341 int flags, struct regmap *grf, int reg,
342 int shift, int width, int mux_flags);
343
320#define PNAME(x) static const char *const x[] __initconst
321
322enum rockchip_clk_branch_type {
323 branch_composite,
324 branch_mux,
344#define PNAME(x) static const char *const x[] __initconst
345
346enum rockchip_clk_branch_type {
347 branch_composite,
348 branch_mux,
349 branch_muxgrf,
325 branch_divider,
326 branch_fraction_divider,
327 branch_gate,
328 branch_mmc,
329 branch_inverter,
330 branch_factor,
331 branch_ddrclk,
332};

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546 .flags = f, \
547 .muxdiv_offset = o, \
548 .mux_shift = s, \
549 .mux_width = w, \
550 .mux_flags = mf, \
551 .gate_offset = -1, \
552 }
553
350 branch_divider,
351 branch_fraction_divider,
352 branch_gate,
353 branch_mmc,
354 branch_inverter,
355 branch_factor,
356 branch_ddrclk,
357};

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571 .flags = f, \
572 .muxdiv_offset = o, \
573 .mux_shift = s, \
574 .mux_width = w, \
575 .mux_flags = mf, \
576 .gate_offset = -1, \
577 }
578
579#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
580 { \
581 .id = _id, \
582 .branch_type = branch_muxgrf, \
583 .name = cname, \
584 .parent_names = pnames, \
585 .num_parents = ARRAY_SIZE(pnames), \
586 .flags = f, \
587 .muxdiv_offset = o, \
588 .mux_shift = s, \
589 .mux_width = w, \
590 .mux_flags = mf, \
591 .gate_offset = -1, \
592 }
593
554#define DIV(_id, cname, pname, f, o, s, w, df) \
555 { \
556 .id = _id, \
557 .branch_type = branch_divider, \
558 .name = cname, \
559 .parent_names = (const char *[]){ pname }, \
560 .num_parents = 1, \
561 .flags = f, \

--- 122 unchanged lines hidden --- 		594#define DIV(_id, cname, pname, f, o, s, w, df) \
595 { \
596 .id = _id, \
597 .branch_type = branch_divider, \
598 .name = cname, \
599 .parent_names = (const char *[]){ pname }, \
600 .num_parents = 1, \
601 .flags = f, \

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