| clk.h (8a76f443a9ea6f7f72ede9f95fe0ca5b90f09a43) | clk.h (3536c97a52db2848d13512878c65affd98fd29db) |
|---|---|
| 1/* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * based on 6 * 7 * samsung/clk.h 8 * Copyright (c) 2013 Samsung Electronics Co., Ltd. --- 43 unchanged lines hidden (view full) --- 52#define RK3288_SDMMC_CON1 0x204 53#define RK3288_SDIO0_CON0 0x208 54#define RK3288_SDIO0_CON1 0x20c 55#define RK3288_SDIO1_CON0 0x210 56#define RK3288_SDIO1_CON1 0x214 57#define RK3288_EMMC_CON0 0x218 58#define RK3288_EMMC_CON1 0x21c 59 | 1/* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * based on 6 * 7 * samsung/clk.h 8 * Copyright (c) 2013 Samsung Electronics Co., Ltd. --- 43 unchanged lines hidden (view full) --- 52#define RK3288_SDMMC_CON1 0x204 53#define RK3288_SDIO0_CON0 0x208 54#define RK3288_SDIO0_CON1 0x20c 55#define RK3288_SDIO1_CON0 0x210 56#define RK3288_SDIO1_CON1 0x214 57#define RK3288_EMMC_CON0 0x218 58#define RK3288_EMMC_CON1 0x21c 59 |
| 60#define RK3368_PLL_CON(x) RK2928_PLL_CON(x) 61#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 62#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 63#define RK3368_GLB_SRST_FST 0x280 64#define RK3368_GLB_SRST_SND 0x284 65#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 66#define RK3368_MISC_CON 0x380 67#define RK3368_SDMMC_CON0 0x400 68#define RK3368_SDMMC_CON1 0x404 69#define RK3368_SDIO0_CON0 0x408 70#define RK3368_SDIO0_CON1 0x40c 71#define RK3368_SDIO1_CON0 0x410 72#define RK3368_SDIO1_CON1 0x414 73#define RK3368_EMMC_CON0 0x418 74#define RK3368_EMMC_CON1 0x41c 75 |
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| 60enum rockchip_pll_type { 61 pll_rk3066, 62}; 63 64#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 65{ \ 66 .rate = _rate##U, \ 67 .nr = _nr, \ --- 400 unchanged lines hidden --- | 76enum rockchip_pll_type { 77 pll_rk3066, 78}; 79 80#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 81{ \ 82 .rate = _rate##U, \ 83 .nr = _nr, \ --- 400 unchanged lines hidden --- |