clk.h (85fa0c7f8d05eb6baf2c122e85d45d928df0992b) clk.h (b9e4ba541607e6ee9c6c8493f51198fe3af03aec)
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.h
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

--- 26 unchanged lines hidden (view full) ---

35#define RK2928_MODE_CON 0x40
36#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
37#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
38#define RK2928_GLB_SRST_FST 0x100
39#define RK2928_GLB_SRST_SND 0x104
40#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134
42
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.h
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

--- 26 unchanged lines hidden (view full) ---

35#define RK2928_MODE_CON 0x40
36#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
37#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
38#define RK2928_GLB_SRST_FST 0x100
39#define RK2928_GLB_SRST_SND 0x104
40#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134
42
43#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44#define RK3288_MODE_CON 0x50
45#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
46#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
47#define RK3288_GLB_SRST_FST 0x1b0
48#define RK3288_GLB_SRST_SND 0x1b4
49#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
50#define RK3288_MISC_CON 0x1e8
51
43enum rockchip_pll_type {
44 pll_rk3066,
45};
46
47#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
48{ \
49 .rate = _rate##U, \
50 .nr = _nr, \

--- 288 unchanged lines hidden --- 		52enum rockchip_pll_type {
53 pll_rk3066,
54};
55
56#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
57{ \
58 .rate = _rate##U, \
59 .nr = _nr, \

--- 288 unchanged lines hidden ---