clk.h (5190c08b29899131a183ea5802b9397918cca1ae) clk.h (307a2e9ac524bbec707c0e2b47ca50adaecc23f2)
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

--- 19 unchanged lines hidden (view full) ---

28
29#include <linux/io.h>
30
31struct clk;
32
33#define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
35
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * based on

--- 19 unchanged lines hidden (view full) ---

28
29#include <linux/io.h>
30
31struct clk;
32
33#define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
35
36/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
36/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
37#define RK2928_PLL_CON(x) ((x) * 0x4)
38#define RK2928_MODE_CON 0x40
39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41#define RK2928_GLB_SRST_FST 0x100
42#define RK2928_GLB_SRST_SND 0x104
43#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44#define RK2928_MISC_CON 0x134
45
46#define RK3036_SDMMC_CON0 0x144
47#define RK3036_SDMMC_CON1 0x148
48#define RK3036_SDIO_CON0 0x14c
49#define RK3036_SDIO_CON1 0x150
50#define RK3036_EMMC_CON0 0x154
51#define RK3036_EMMC_CON1 0x158
52
37#define RK2928_PLL_CON(x) ((x) * 0x4)
38#define RK2928_MODE_CON 0x40
39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41#define RK2928_GLB_SRST_FST 0x100
42#define RK2928_GLB_SRST_SND 0x104
43#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44#define RK2928_MISC_CON 0x134
45
46#define RK3036_SDMMC_CON0 0x144
47#define RK3036_SDMMC_CON1 0x148
48#define RK3036_SDIO_CON0 0x14c
49#define RK3036_SDIO_CON1 0x150
50#define RK3036_EMMC_CON0 0x154
51#define RK3036_EMMC_CON1 0x158
52
53#define RK3228_GLB_SRST_FST 0x1f0
54#define RK3228_GLB_SRST_SND 0x1f4
55#define RK3228_SDMMC_CON0 0x1c0
56#define RK3228_SDMMC_CON1 0x1c4
57#define RK3228_SDIO_CON0 0x1c8
58#define RK3228_SDIO_CON1 0x1cc
59#define RK3228_EMMC_CON0 0x1d8
60#define RK3228_EMMC_CON1 0x1dc
61
53#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
54#define RK3288_MODE_CON 0x50
55#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
56#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
57#define RK3288_GLB_SRST_FST 0x1b0
58#define RK3288_GLB_SRST_SND 0x1b4
59#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
60#define RK3288_MISC_CON 0x1e8

--- 453 unchanged lines hidden --- 		62#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
63#define RK3288_MODE_CON 0x50
64#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
65#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
66#define RK3288_GLB_SRST_FST 0x1b0
67#define RK3288_GLB_SRST_SND 0x1b4
68#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
69#define RK3288_MISC_CON 0x1e8

--- 453 unchanged lines hidden ---