| Kconfig (3fd6c59042dbba50391e30862beac979491145fe) | Kconfig (3b42450ce1771c7b11d8f3563f4bbfe9b8d26611) |
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| 1# SPDX-License-Identifier: GPL-2.0 2 3config CLK_RENESAS 4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS 5 default y if ARCH_RENESAS 6 select CLK_EMEV2 if ARCH_EMEV2 7 select CLK_RZA1 if ARCH_R7S72100 8 select CLK_R7S9210 if ARCH_R7S9210 --- 223 unchanged lines hidden (view full) --- 232config CLK_RZG2L 233 bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST 234 select RESET_CONTROLLER 235 236config CLK_RZV2H 237 bool "RZ/V2H(P) family clock support" if COMPILE_TEST 238 select RESET_CONTROLLER 239 | 1# SPDX-License-Identifier: GPL-2.0 2 3config CLK_RENESAS 4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS 5 default y if ARCH_RENESAS 6 select CLK_EMEV2 if ARCH_EMEV2 7 select CLK_RZA1 if ARCH_R7S72100 8 select CLK_R7S9210 if ARCH_R7S9210 --- 223 unchanged lines hidden (view full) --- 232config CLK_RZG2L 233 bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST 234 select RESET_CONTROLLER 235 236config CLK_RZV2H 237 bool "RZ/V2H(P) family clock support" if COMPILE_TEST 238 select RESET_CONTROLLER 239 |
| 240config CLK_RENESAS_VBATTB 241 tristate "Renesas VBATTB clock controller" 242 depends on ARCH_RZG2L || COMPILE_TEST 243 select RESET_CONTROLLER 244 |
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| 240# Generic 241config CLK_RENESAS_CPG_MSSR 242 bool "CPG/MSSR clock support" if COMPILE_TEST 243 select CLK_RENESAS_DIV6 244 245config CLK_RENESAS_CPG_MSTP 246 bool "MSTP clock support" if COMPILE_TEST 247 248config CLK_RENESAS_DIV6 249 bool "DIV6 clock support" if COMPILE_TEST 250 251endif # CLK_RENESAS | 245# Generic 246config CLK_RENESAS_CPG_MSSR 247 bool "CPG/MSSR clock support" if COMPILE_TEST 248 select CLK_RENESAS_DIV6 249 250config CLK_RENESAS_CPG_MSTP 251 bool "MSTP clock support" if COMPILE_TEST 252 253config CLK_RENESAS_DIV6 254 bool "DIV6 clock support" if COMPILE_TEST 255 256endif # CLK_RENESAS |