clk-pll.c (ec623f2a43ebe482abc925f8785f462c0fe3c08a) clk-pll.c (4a47295144ddbcf802fcddb3d7c0736d9a1f2e40)
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *

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48
49static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
50 unsigned long parent_rate)
51{
52 struct meson_clk_pll *pll = to_meson_clk_pll(hw);
53 struct parm *p;
54 unsigned long parent_rate_mhz = parent_rate / 1000000;
55 unsigned long rate_mhz;
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *

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48
49static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
50 unsigned long parent_rate)
51{
52 struct meson_clk_pll *pll = to_meson_clk_pll(hw);
53 struct parm *p;
54 unsigned long parent_rate_mhz = parent_rate / 1000000;
55 unsigned long rate_mhz;
56 u16 n, m, od;
56 u16 n, m, frac = 0, od, od2 = 0;
57 u32 reg;
58
59 p = &pll->n;
60 reg = readl(pll->base + p->reg_off);
61 n = PARM_GET(p->width, p->shift, reg);
62
63 p = &pll->m;
64 reg = readl(pll->base + p->reg_off);
65 m = PARM_GET(p->width, p->shift, reg);
66
67 p = &pll->od;
68 reg = readl(pll->base + p->reg_off);
69 od = PARM_GET(p->width, p->shift, reg);
70
57 u32 reg;
58
59 p = &pll->n;
60 reg = readl(pll->base + p->reg_off);
61 n = PARM_GET(p->width, p->shift, reg);
62
63 p = &pll->m;
64 reg = readl(pll->base + p->reg_off);
65 m = PARM_GET(p->width, p->shift, reg);
66
67 p = &pll->od;
68 reg = readl(pll->base + p->reg_off);
69 od = PARM_GET(p->width, p->shift, reg);
70
71 rate_mhz = (parent_rate_mhz * m / n) >> od;
71 p = &pll->od2;
72 if (p->width) {
73 reg = readl(pll->base + p->reg_off);
74 od2 = PARM_GET(p->width, p->shift, reg);
75 }
72
76
77 p = &pll->frac;
78 if (p->width) {
79 reg = readl(pll->base + p->reg_off);
80 frac = PARM_GET(p->width, p->shift, reg);
81 rate_mhz = (parent_rate_mhz * m + \
82 (parent_rate_mhz * frac >> 12)) * 2 / n;
83 rate_mhz = rate_mhz >> od >> od2;
84 } else
85 rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
86
73 return rate_mhz * 1000000;
74}
75
76static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
77 unsigned long *parent_rate)
78{
79 struct meson_clk_pll *pll = to_meson_clk_pll(hw);
80 const struct pll_rate_table *rate_table = pll->rate_table;

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150 reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
151 writel(reg, pll->base + p->reg_off);
152
153 p = &pll->od;
154 reg = readl(pll->base + p->reg_off);
155 reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
156 writel(reg, pll->base + p->reg_off);
157
87 return rate_mhz * 1000000;
88}
89
90static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
91 unsigned long *parent_rate)
92{
93 struct meson_clk_pll *pll = to_meson_clk_pll(hw);
94 const struct pll_rate_table *rate_table = pll->rate_table;

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164 reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
165 writel(reg, pll->base + p->reg_off);
166
167 p = &pll->od;
168 reg = readl(pll->base + p->reg_off);
169 reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
170 writel(reg, pll->base + p->reg_off);
171
172 p = &pll->od2;
173 if (p->width) {
174 reg = readl(pll->base + p->reg_off);
175 reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
176 writel(reg, pll->base + p->reg_off);
177 }
178
179 p = &pll->frac;
180 if (p->width) {
181 reg = readl(pll->base + p->reg_off);
182 reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
183 writel(reg, pll->base + p->reg_off);
184 }
185
158 p = &pll->n;
159 ret = meson_clk_pll_wait_lock(pll, p);
160 if (ret) {
161 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
162 __func__, old_rate);
163 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
164 }
165

--- 12 unchanged lines hidden --- 		186 p = &pll->n;
187 ret = meson_clk_pll_wait_lock(pll, p);
188 if (ret) {
189 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
190 __func__, old_rate);
191 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
192 }
193

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