clk-pll.c (afeea2758b4f1210361ce2a91d8fa3e7df606ad2) clk-pll.c (d4c83ac16c6532bda5d9a9d95a30b7dfff494b43)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 *
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
8 */

--- 275 unchanged lines hidden (view full) ---

284 return 0;
285
286 udelay(20);
287 } while (--delay);
288
289 return -ETIMEDOUT;
290}
291
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 *
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
8 */

--- 275 unchanged lines hidden (view full) ---

284 return 0;
285
286 udelay(20);
287 } while (--delay);
288
289 return -ETIMEDOUT;
290}
291
292static int meson_clk_pll_is_enabled(struct clk_hw *hw)
293{
294 struct clk_regmap *clk = to_clk_regmap(hw);
295 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
296
297 if (MESON_PARM_APPLICABLE(&pll->rst) &&
298 meson_parm_read(clk->map, &pll->rst))
299 return 0;
300
301 if (!meson_parm_read(clk->map, &pll->en) ||
302 !meson_parm_read(clk->map, &pll->l))
303 return 0;
304
305 return 1;
306}
307
292static int meson_clk_pll_init(struct clk_hw *hw)
293{
294 struct clk_regmap *clk = to_clk_regmap(hw);
295 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
296
308static int meson_clk_pll_init(struct clk_hw *hw)
309{
310 struct clk_regmap *clk = to_clk_regmap(hw);
311 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
312
313 /*
314 * Keep the clock running, which was already initialized and enabled
315 * from the bootloader stage, to avoid any glitches.
316 */
317 if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
318 meson_clk_pll_is_enabled(hw))
319 return 0;
320
297 if (pll->init_count) {
298 if (MESON_PARM_APPLICABLE(&pll->rst))
299 meson_parm_write(clk->map, &pll->rst, 1);
300
301 regmap_multi_reg_write(clk->map, pll->init_regs,
302 pll->init_count);
303
304 if (MESON_PARM_APPLICABLE(&pll->rst))
305 meson_parm_write(clk->map, &pll->rst, 0);
306 }
307
308 return 0;
309}
310
321 if (pll->init_count) {
322 if (MESON_PARM_APPLICABLE(&pll->rst))
323 meson_parm_write(clk->map, &pll->rst, 1);
324
325 regmap_multi_reg_write(clk->map, pll->init_regs,
326 pll->init_count);
327
328 if (MESON_PARM_APPLICABLE(&pll->rst))
329 meson_parm_write(clk->map, &pll->rst, 0);
330 }
331
332 return 0;
333}
334
311static int meson_clk_pll_is_enabled(struct clk_hw *hw)
312{
313 struct clk_regmap *clk = to_clk_regmap(hw);
314 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
315
316 if (MESON_PARM_APPLICABLE(&pll->rst) &&
317 meson_parm_read(clk->map, &pll->rst))
318 return 0;
319
320 if (!meson_parm_read(clk->map, &pll->en) ||
321 !meson_parm_read(clk->map, &pll->l))
322 return 0;
323
324 return 1;
325}
326
327static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
328{
329 int retries = 10;
330
331 do {
332 meson_clk_pll_init(hw);
333 if (!meson_clk_pll_wait_lock(hw))
334 return 0;

--- 155 unchanged lines hidden --- 		335static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
336{
337 int retries = 10;
338
339 do {
340 meson_clk_pll_init(hw);
341 if (!meson_clk_pll_wait_lock(hw))
342 return 0;

--- 155 unchanged lines hidden ---