axg.c (2863b00941bc3062ea3299ed4057acfd9e52c335) axg.c (e40c7e3cda07099a92ea68d022f3304c14f9659f)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * AmLogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.

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19
20#include "clkc.h"
21#include "axg.h"
22
23static DEFINE_SPINLOCK(meson_clk_lock);
24
25static struct clk_regmap axg_fixed_pll = {
26 .data = &(struct meson_clk_pll_data){
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * AmLogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.

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19
20#include "clkc.h"
21#include "axg.h"
22
23static DEFINE_SPINLOCK(meson_clk_lock);
24
25static struct clk_regmap axg_fixed_pll = {
26 .data = &(struct meson_clk_pll_data){
27 .en = {
28 .reg_off = HHI_MPLL_CNTL,
29 .shift = 30,
30 .width = 1,
31 },
27 .m = {
28 .reg_off = HHI_MPLL_CNTL,
29 .shift = 0,
30 .width = 9,
31 },
32 .n = {
33 .reg_off = HHI_MPLL_CNTL,
34 .shift = 9,

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60 .ops = &meson_clk_pll_ro_ops,
61 .parent_names = (const char *[]){ "xtal" },
62 .num_parents = 1,
63 },
64};
65
66static struct clk_regmap axg_sys_pll = {
67 .data = &(struct meson_clk_pll_data){
32 .m = {
33 .reg_off = HHI_MPLL_CNTL,
34 .shift = 0,
35 .width = 9,
36 },
37 .n = {
38 .reg_off = HHI_MPLL_CNTL,
39 .shift = 9,

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65 .ops = &meson_clk_pll_ro_ops,
66 .parent_names = (const char *[]){ "xtal" },
67 .num_parents = 1,
68 },
69};
70
71static struct clk_regmap axg_sys_pll = {
72 .data = &(struct meson_clk_pll_data){
73 .en = {
74 .reg_off = HHI_SYS_PLL_CNTL,
75 .shift = 30,
76 .width = 1,
77 },
68 .m = {
69 .reg_off = HHI_SYS_PLL_CNTL,
70 .shift = 0,
71 .width = 9,
72 },
73 .n = {
74 .reg_off = HHI_SYS_PLL_CNTL,
75 .shift = 9,

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192};
193
194static const struct reg_sequence axg_gp0_init_regs[] = {
195 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
196 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
197 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
198 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
199 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
78 .m = {
79 .reg_off = HHI_SYS_PLL_CNTL,
80 .shift = 0,
81 .width = 9,
82 },
83 .n = {
84 .reg_off = HHI_SYS_PLL_CNTL,
85 .shift = 9,

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202};
203
204static const struct reg_sequence axg_gp0_init_regs[] = {
205 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
206 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
207 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
208 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
209 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
200 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
201};
202
203static struct clk_regmap axg_gp0_pll = {
204 .data = &(struct meson_clk_pll_data){
210};
211
212static struct clk_regmap axg_gp0_pll = {
213 .data = &(struct meson_clk_pll_data){
214 .en = {
215 .reg_off = HHI_GP0_PLL_CNTL,
216 .shift = 30,
217 .width = 1,
218 },
205 .m = {
206 .reg_off = HHI_GP0_PLL_CNTL,
207 .shift = 0,
208 .width = 9,
209 },
210 .n = {
211 .reg_off = HHI_GP0_PLL_CNTL,
212 .shift = 9,

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245};
246
247static const struct reg_sequence axg_hifi_init_regs[] = {
248 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
249 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
250 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
251 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
252 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
219 .m = {
220 .reg_off = HHI_GP0_PLL_CNTL,
221 .shift = 0,
222 .width = 9,
223 },
224 .n = {
225 .reg_off = HHI_GP0_PLL_CNTL,
226 .shift = 9,

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259};
260
261static const struct reg_sequence axg_hifi_init_regs[] = {
262 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
263 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
264 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
265 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
266 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
253 { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
254};
255
256static struct clk_regmap axg_hifi_pll = {
257 .data = &(struct meson_clk_pll_data){
267};
268
269static struct clk_regmap axg_hifi_pll = {
270 .data = &(struct meson_clk_pll_data){
271 .en = {
272 .reg_off = HHI_HIFI_PLL_CNTL,
273 .shift = 30,
274 .width = 1,
275 },
258 .m = {
259 .reg_off = HHI_HIFI_PLL_CNTL,
260 .shift = 0,
261 .width = 9,
262 },
263 .n = {
264 .reg_off = HHI_HIFI_PLL_CNTL,
265 .shift = 9,

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632 .n = 3,
633 .od = 1,
634 .od2 = 3,
635 },
636 { /* sentinel */ },
637};
638
639static const struct reg_sequence axg_pcie_init_regs[] = {
276 .m = {
277 .reg_off = HHI_HIFI_PLL_CNTL,
278 .shift = 0,
279 .width = 9,
280 },
281 .n = {
282 .reg_off = HHI_HIFI_PLL_CNTL,
283 .shift = 9,

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650 .n = 3,
651 .od = 1,
652 .od2 = 3,
653 },
654 { /* sentinel */ },
655};
656
657static const struct reg_sequence axg_pcie_init_regs[] = {
640 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
641 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
642 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
643 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
644 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
645 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
646 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
647};
648
649static struct clk_regmap axg_pcie_pll = {
650 .data = &(struct meson_clk_pll_data){
658 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
659 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
660 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
661 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
662 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
663 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
664};
665
666static struct clk_regmap axg_pcie_pll = {
667 .data = &(struct meson_clk_pll_data){
668 .en = {
669 .reg_off = HHI_PCIE_PLL_CNTL,
670 .shift = 30,
671 .width = 1,
672 },
651 .m = {
652 .reg_off = HHI_PCIE_PLL_CNTL,
653 .shift = 0,
654 .width = 9,
655 },
656 .n = {
657 .reg_off = HHI_PCIE_PLL_CNTL,
658 .shift = 9,

--- 587 unchanged lines hidden --- 		673 .m = {
674 .reg_off = HHI_PCIE_PLL_CNTL,
675 .shift = 0,
676 .width = 9,
677 },
678 .n = {
679 .reg_off = HHI_PCIE_PLL_CNTL,
680 .shift = 9,

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