clk-mt6779.c (d3d6bd5e25cdc460df33ae1db4f051c4bdd3aa60) | clk-mt6779.c (0f69a423c458f0a6586b7e4ac99e9c2d901ecf56) |
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1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.com> 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> --- 866 unchanged lines hidden (view full) --- 875#define GATE_INFRA2(_id, _name, _parent, _shift) \ 876 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 877 &mtk_clk_gate_ops_setclr) 878#define GATE_INFRA3(_id, _name, _parent, _shift) \ 879 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 880 &mtk_clk_gate_ops_setclr) 881 882static const struct mtk_gate infra_clks[] = { | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.com> 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> --- 866 unchanged lines hidden (view full) --- 875#define GATE_INFRA2(_id, _name, _parent, _shift) \ 876 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 877 &mtk_clk_gate_ops_setclr) 878#define GATE_INFRA3(_id, _name, _parent, _shift) \ 879 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 880 &mtk_clk_gate_ops_setclr) 881 882static const struct mtk_gate infra_clks[] = { |
883 GATE_DUMMY(CLK_DUMMY, "ifa_dummy"), |
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883 /* INFRA0 */ 884 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 885 "axi_sel", 0), 886 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 887 "axi_sel", 1), 888 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 889 "axi_sel", 2), 890 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", --- 363 unchanged lines hidden (view full) --- 1254 1255 mtk_clk_register_composites(&pdev->dev, top_aud_divs, 1256 ARRAY_SIZE(top_aud_divs), base, 1257 &mt6779_clk_lock, clk_data); 1258 1259 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1260} 1261 | 884 /* INFRA0 */ 885 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 886 "axi_sel", 0), 887 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 888 "axi_sel", 1), 889 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 890 "axi_sel", 2), 891 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", --- 363 unchanged lines hidden (view full) --- 1255 1256 mtk_clk_register_composites(&pdev->dev, top_aud_divs, 1257 ARRAY_SIZE(top_aud_divs), base, 1258 &mt6779_clk_lock, clk_data); 1259 1260 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1261} 1262 |
1262static int clk_mt6779_infra_probe(struct platform_device *pdev) 1263{ 1264 struct clk_hw_onecell_data *clk_data; 1265 struct device_node *node = pdev->dev.of_node; 1266 1267 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1268 1269 mtk_clk_register_gates(&pdev->dev, node, infra_clks, 1270 ARRAY_SIZE(infra_clks), clk_data); 1271 1272 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1273} 1274 | |
1275static const struct of_device_id of_match_clk_mt6779[] = { 1276 { 1277 .compatible = "mediatek,mt6779-apmixed", 1278 .data = clk_mt6779_apmixed_probe, 1279 }, { 1280 .compatible = "mediatek,mt6779-topckgen", 1281 .data = clk_mt6779_top_probe, 1282 }, { | 1263static const struct of_device_id of_match_clk_mt6779[] = { 1264 { 1265 .compatible = "mediatek,mt6779-apmixed", 1266 .data = clk_mt6779_apmixed_probe, 1267 }, { 1268 .compatible = "mediatek,mt6779-topckgen", 1269 .data = clk_mt6779_top_probe, 1270 }, { |
1283 .compatible = "mediatek,mt6779-infracfg_ao", 1284 .data = clk_mt6779_infra_probe, 1285 }, { | |
1286 /* sentinel */ 1287 } 1288}; 1289 1290static int clk_mt6779_probe(struct platform_device *pdev) 1291{ 1292 int (*clk_probe)(struct platform_device *pdev); 1293 int r; --- 6 unchanged lines hidden (view full) --- 1300 if (r) 1301 dev_err(&pdev->dev, 1302 "could not register clock provider: %s: %d\n", 1303 pdev->name, r); 1304 1305 return r; 1306} 1307 | 1271 /* sentinel */ 1272 } 1273}; 1274 1275static int clk_mt6779_probe(struct platform_device *pdev) 1276{ 1277 int (*clk_probe)(struct platform_device *pdev); 1278 int r; --- 6 unchanged lines hidden (view full) --- 1285 if (r) 1286 dev_err(&pdev->dev, 1287 "could not register clock provider: %s: %d\n", 1288 pdev->name, r); 1289 1290 return r; 1291} 1292 |
1293static const struct mtk_clk_desc infra_desc = { 1294 .clks = infra_clks, 1295 .num_clks = ARRAY_SIZE(infra_clks), 1296}; 1297 1298static const struct of_device_id of_match_clk_mt6779_infra[] = { 1299 { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, 1300 { /* sentinel */ } 1301}; 1302 1303static struct platform_driver clk_mt6779_infra_drv = { 1304 .probe = mtk_clk_simple_probe, 1305 .remove = mtk_clk_simple_remove, 1306 .driver = { 1307 .name = "clk-mt6779-infra", 1308 .of_match_table = of_match_clk_mt6779_infra, 1309 }, 1310}; 1311 |
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1308static struct platform_driver clk_mt6779_drv = { 1309 .probe = clk_mt6779_probe, 1310 .driver = { 1311 .name = "clk-mt6779", 1312 .of_match_table = of_match_clk_mt6779, 1313 }, 1314}; 1315 1316static int __init clk_mt6779_init(void) 1317{ | 1312static struct platform_driver clk_mt6779_drv = { 1313 .probe = clk_mt6779_probe, 1314 .driver = { 1315 .name = "clk-mt6779", 1316 .of_match_table = of_match_clk_mt6779, 1317 }, 1318}; 1319 1320static int __init clk_mt6779_init(void) 1321{ |
1318 return platform_driver_register(&clk_mt6779_drv); | 1322 int ret = platform_driver_register(&clk_mt6779_drv); 1323 1324 if (ret) 1325 return ret; 1326 return platform_driver_register(&clk_mt6779_infra_drv); |
1319} 1320 1321arch_initcall(clk_mt6779_init); 1322MODULE_LICENSE("GPL"); | 1327} 1328 1329arch_initcall(clk_mt6779_init); 1330MODULE_LICENSE("GPL"); |