x1000-cgu.c (98817a84ff1c755c347ac633ff017a623a631fad) x1000-cgu.c (82df5b7329aaeb21b3e8fc86fa2d62a3d68602aa)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * X1000 SoC CGU driver
4 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/delay.h>

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273 },
274
275 [X1000_CLK_SSIMUX] = {
276 "ssi_mux", CGU_CLK_MUX,
277 .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
278 .mux = { CGU_REG_SSICDR, 30, 1 },
279 },
280
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * X1000 SoC CGU driver
4 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/delay.h>

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273 },
274
275 [X1000_CLK_SSIMUX] = {
276 "ssi_mux", CGU_CLK_MUX,
277 .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
278 .mux = { CGU_REG_SSICDR, 30, 1 },
279 },
280
281 [X1000_CLK_EXCLK_DIV512] = {
282 "exclk_div512", CGU_CLK_FIXDIV,
283 .parents = { X1000_CLK_EXCLK },
284 .fixdiv = { 512 },
285 },
286
287 [X1000_CLK_RTC] = {
288 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
289 .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
290 .mux = { CGU_REG_OPCR, 2, 1},
291 .gate = { CGU_REG_CLKGR, 27 },
292 },
293
281 /* Gate-only clocks */
282
283 [X1000_CLK_EMC] = {
284 "emc", CGU_CLK_GATE,
285 .parents = { X1000_CLK_AHB2, -1, -1, -1 },
286 .gate = { CGU_REG_CLKGR, 0 },
287 },
288

--- 97 unchanged lines hidden --- 		294 /* Gate-only clocks */
295
296 [X1000_CLK_EMC] = {
297 "emc", CGU_CLK_GATE,
298 .parents = { X1000_CLK_AHB2, -1, -1, -1 },
299 .gate = { CGU_REG_CLKGR, 0 },
300 },
301

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