jz4780-cgu.c (9b031c86506cef9acae45e61339fcf9deaabb793) jz4780-cgu.c (82df5b7329aaeb21b3e8fc86fa2d62a3d68602aa)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ingenic JZ4780 SoC CGU driver
4 *
5 * Copyright (c) 2013-2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/of.h>
14
15#include <dt-bindings/clock/jz4780-cgu.h>
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ingenic JZ4780 SoC CGU driver
4 *
5 * Copyright (c) 2013-2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/of.h>
14
15#include <dt-bindings/clock/jz4780-cgu.h>
16
16#include "cgu.h"
17#include "pm.h"
18
19/* CGU register offsets */
20#define CGU_REG_CLOCKCONTROL 0x00
21#define CGU_REG_LCR 0x04
22#define CGU_REG_APLL 0x10
23#define CGU_REG_MPLL 0x14

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261
262 [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
263 [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
264
265 /* PLLs */
266
267#define DEF_PLL(name) { \
268 .reg = CGU_REG_ ## name, \
17#include "cgu.h"
18#include "pm.h"
19
20/* CGU register offsets */
21#define CGU_REG_CLOCKCONTROL 0x00
22#define CGU_REG_LCR 0x04
23#define CGU_REG_APLL 0x10
24#define CGU_REG_MPLL 0x14

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262
263 [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
264 [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
265
266 /* PLLs */
267
268#define DEF_PLL(name) { \
269 .reg = CGU_REG_ ## name, \
270 .rate_multiplier = 1, \
269 .m_shift = 19, \
270 .m_bits = 13, \
271 .m_offset = 1, \
272 .n_shift = 13, \
273 .n_bits = 6, \
274 .n_offset = 1, \
275 .od_shift = 9, \
276 .od_bits = 4, \
277 .od_max = 16, \
278 .od_encoding = pll_od_encoding, \
279 .stable_bit = 6, \
271 .m_shift = 19, \
272 .m_bits = 13, \
273 .m_offset = 1, \
274 .n_shift = 13, \
275 .n_bits = 6, \
276 .n_offset = 1, \
277 .od_shift = 9, \
278 .od_bits = 4, \
279 .od_max = 16, \
280 .od_encoding = pll_od_encoding, \
281 .stable_bit = 6, \
282 .bypass_reg = CGU_REG_ ## name, \
280 .bypass_bit = 1, \
281 .enable_bit = 0, \
282}
283
284 [JZ4780_CLK_APLL] = {
285 "apll", CGU_CLK_PLL,
286 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
287 .pll = DEF_PLL(APLL),

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508 "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
509 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
510 JZ4780_CLK_EPLL },
511 .mux = { CGU_REG_BCHCDR, 30, 2 },
512 .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
513 .gate = { CGU_REG_CLKGR0, 1 },
514 },
515
283 .bypass_bit = 1, \
284 .enable_bit = 0, \
285}
286
287 [JZ4780_CLK_APLL] = {
288 "apll", CGU_CLK_PLL,
289 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
290 .pll = DEF_PLL(APLL),

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511 "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
512 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
513 JZ4780_CLK_EPLL },
514 .mux = { CGU_REG_BCHCDR, 30, 2 },
515 .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
516 .gate = { CGU_REG_CLKGR0, 1 },
517 },
518
519 [JZ4780_CLK_EXCLK_DIV512] = {
520 "exclk_div512", CGU_CLK_FIXDIV,
521 .parents = { JZ4780_CLK_EXCLK },
522 .fixdiv = { 512 },
523 },
524
525 [JZ4780_CLK_RTC] = {
526 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
527 .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
528 .mux = { CGU_REG_OPCR, 2, 1},
529 },
530
516 /* Gate-only clocks */
517
518 [JZ4780_CLK_NEMC] = {
519 "nemc", CGU_CLK_GATE,
520 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
521 .gate = { CGU_REG_CLKGR0, 0 },
522 },
523

--- 250 unchanged lines hidden --- 		531 /* Gate-only clocks */
532
533 [JZ4780_CLK_NEMC] = {
534 "nemc", CGU_CLK_GATE,
535 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
536 .gate = { CGU_REG_CLKGR0, 0 },
537 },
538

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