jz4770-cgu.c (44b06a76ad330f327fe2366472a83d7d1d06d86e) jz4770-cgu.c (2ee93e3c953b7263c21ce61e7c42e33d0539bef9)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * JZ4770 SoC CGU driver
4 * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
5 */
6
7#include <linux/bitops.h>
8#include <linux/clk-provider.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/of.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * JZ4770 SoC CGU driver
4 * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
5 */
6
7#include <linux/bitops.h>
8#include <linux/clk-provider.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/of.h>
12#include <linux/syscore_ops.h>
13#include <dt-bindings/clock/jz4770-cgu.h>
14#include "cgu.h"
12#include <dt-bindings/clock/jz4770-cgu.h>
13#include "cgu.h"
14#include "pm.h"
15
16/*
17 * CPM registers offset address definition
18 */
19#define CGU_REG_CPCCR 0x00
20#define CGU_REG_LCR 0x04
21#define CGU_REG_CPPCR0 0x10
22#define CGU_REG_CLKGR0 0x20

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33#define CGU_REG_CIMCDR 0x7c
34#define CGU_REG_GPSCDR 0x80
35#define CGU_REG_PCMCDR 0x84
36#define CGU_REG_GPUCDR 0x88
37#define CGU_REG_MSC1CDR 0xA4
38#define CGU_REG_MSC2CDR 0xA8
39#define CGU_REG_BCHCDR 0xAC
40
15
16/*
17 * CPM registers offset address definition
18 */
19#define CGU_REG_CPCCR 0x00
20#define CGU_REG_LCR 0x04
21#define CGU_REG_CPPCR0 0x10
22#define CGU_REG_CLKGR0 0x20

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33#define CGU_REG_CIMCDR 0x7c
34#define CGU_REG_GPSCDR 0x80
35#define CGU_REG_PCMCDR 0x84
36#define CGU_REG_GPUCDR 0x88
37#define CGU_REG_MSC1CDR 0xA4
38#define CGU_REG_MSC2CDR 0xA8
39#define CGU_REG_BCHCDR 0xAC
40
41/* bits within the LCR register */
42#define LCR_LPM BIT(0) /* Low Power Mode */
43
44/* bits within the OPCR register */
45#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
46
47/* bits within the USBPCR1 register */
48#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
49
50static struct ingenic_cgu *cgu;
51

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424
425 [JZ4770_CLK_RTC] = {
426 "rtc", CGU_CLK_MUX,
427 .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
428 .mux = { CGU_REG_OPCR, 2, 1},
429 },
430};
431
41/* bits within the OPCR register */
42#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
43
44/* bits within the USBPCR1 register */
45#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
46
47static struct ingenic_cgu *cgu;
48

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421
422 [JZ4770_CLK_RTC] = {
423 "rtc", CGU_CLK_MUX,
424 .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
425 .mux = { CGU_REG_OPCR, 2, 1},
426 },
427};
428
432#if IS_ENABLED(CONFIG_PM_SLEEP)
433static int jz4770_cgu_pm_suspend(void)
434{
435 u32 val;
436
437 val = readl(cgu->base + CGU_REG_LCR);
438 writel(val | LCR_LPM, cgu->base + CGU_REG_LCR);
439 return 0;
440}
441
442static void jz4770_cgu_pm_resume(void)
443{
444 u32 val;
445
446 val = readl(cgu->base + CGU_REG_LCR);
447 writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR);
448}
449
450static struct syscore_ops jz4770_cgu_pm_ops = {
451 .suspend = jz4770_cgu_pm_suspend,
452 .resume = jz4770_cgu_pm_resume,
453};
454#endif /* CONFIG_PM_SLEEP */
455
456static void __init jz4770_cgu_init(struct device_node *np)
457{
458 int retval;
459
460 cgu = ingenic_cgu_new(jz4770_cgu_clocks,
461 ARRAY_SIZE(jz4770_cgu_clocks), np);
462 if (!cgu)
463 pr_err("%s: failed to initialise CGU\n", __func__);
464
465 retval = ingenic_cgu_register_clocks(cgu);
466 if (retval)
467 pr_err("%s: failed to register CGU Clocks\n", __func__);
468
429static void __init jz4770_cgu_init(struct device_node *np)
430{
431 int retval;
432
433 cgu = ingenic_cgu_new(jz4770_cgu_clocks,
434 ARRAY_SIZE(jz4770_cgu_clocks), np);
435 if (!cgu)
436 pr_err("%s: failed to initialise CGU\n", __func__);
437
438 retval = ingenic_cgu_register_clocks(cgu);
439 if (retval)
440 pr_err("%s: failed to register CGU Clocks\n", __func__);
441
469#if IS_ENABLED(CONFIG_PM_SLEEP)
470 register_syscore_ops(&jz4770_cgu_pm_ops);
471#endif
442 ingenic_cgu_register_syscore_ops(cgu);
472}
473
474/* We only probe via devicetree, no need for a platform driver */
475CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
443}
444
445/* We only probe via devicetree, no need for a platform driver */
446CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);