| clk.h (2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c) | clk.h (0836c8604a0bfaed2396d7e2aecb4146f8c07cca) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __MACH_IMX_CLK_H 3#define __MACH_IMX_CLK_H 4 5#include <linux/bits.h> 6#include <linux/spinlock.h> 7#include <linux/clk-provider.h> 8 --- 437 unchanged lines hidden (view full) --- 446 int num_parents, 447 void __iomem *reg, 448 u32 domain_id, 449 unsigned long flags); 450#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ 451 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ 452 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 453 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __MACH_IMX_CLK_H 3#define __MACH_IMX_CLK_H 4 5#include <linux/bits.h> 6#include <linux/spinlock.h> 7#include <linux/clk-provider.h> 8 --- 437 unchanged lines hidden (view full) --- 446 int num_parents, 447 void __iomem *reg, 448 u32 domain_id, 449 unsigned long flags); 450#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ 451 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ 452 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 453 |
| 454struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, 455 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, 456 u32 mask, u32 domain_id, unsigned int *share_count); 457 |
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| 454struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, 455 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 456 u8 clk_divider_flags, const struct clk_div_table *table, 457 spinlock_t *lock); 458#endif | 458struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, 459 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 460 u8 clk_divider_flags, const struct clk_div_table *table, 461 spinlock_t *lock); 462#endif |