clk.h (11994196178d9038d659c2b9468d7c219b708a37) clk.h (1b26cb8a77a49d8f8b5b723ef1db4cd6d2434dfc)
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __MACH_IMX_CLK_H
3#define __MACH_IMX_CLK_H
4
5#include <linux/bits.h>
6#include <linux/spinlock.h>
7#include <linux/clk-provider.h>
8

--- 58 unchanged lines hidden (view full) ---

67 int rate_count;
68 int flags;
69};
70
71extern struct imx_pll14xx_clk imx_1416x_pll;
72extern struct imx_pll14xx_clk imx_1443x_pll;
73extern struct imx_pll14xx_clk imx_1443x_dram_pll;
74
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __MACH_IMX_CLK_H
3#define __MACH_IMX_CLK_H
4
5#include <linux/bits.h>
6#include <linux/spinlock.h>
7#include <linux/clk-provider.h>
8

--- 58 unchanged lines hidden (view full) ---

67 int rate_count;
68 int flags;
69};
70
71extern struct imx_pll14xx_clk imx_1416x_pll;
72extern struct imx_pll14xx_clk imx_1443x_pll;
73extern struct imx_pll14xx_clk imx_1443x_dram_pll;
74
75/* NOTE: Rate table should be kept sorted in descending order. */
76struct imx_fracn_gppll_rate_table {
77 unsigned int rate;
78 unsigned int mfi;
79 unsigned int mfn;
80 unsigned int mfd;
81 unsigned int rdiv;
82 unsigned int odiv;
83};
84
85struct imx_fracn_gppll_clk {
86 const struct imx_fracn_gppll_rate_table *rate_table;
87 int rate_count;
88 int flags;
89};
90
91struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
92 const struct imx_fracn_gppll_clk *pll_clk);
93
94extern struct imx_fracn_gppll_clk imx_fracn_gppll;
95
75#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
76 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
77
78#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
79 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
80 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
81 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
82

--- 353 unchanged lines hidden --- 		96#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
97 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
98
99#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
100 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
101 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
102 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
103

--- 353 unchanged lines hidden ---