clk-imx8qxp.c (91e916771de0abaf58094aa9375cd0227eca102a) clk-imx8qxp.c (5964012ce37e66d2588a9bc82f7184a008851cac)
1// SPDX-License-Identifier: GPL-2.0+
2/*
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
3 * Copyright 2018-2021 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14
15#include "clk-scu.h"
16
17#include <dt-bindings/firmware/imx/rsrc.h>
18
19static const char *dc0_sels[] = {
20 "clk_dummy",
21 "clk_dummy",
22 "dc0_pll0_clk",
23 "dc0_pll1_clk",
24 "dc0_bypass0_clk",
25};
26
27static int imx8qxp_clk_probe(struct platform_device *pdev)
28{
29 struct device_node *ccm_node = pdev->dev.of_node;
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15
16#include "clk-scu.h"
17
18#include <dt-bindings/firmware/imx/rsrc.h>
19
20static const char *dc0_sels[] = {
21 "clk_dummy",
22 "clk_dummy",
23 "dc0_pll0_clk",
24 "dc0_pll1_clk",
25 "dc0_bypass0_clk",
26};
27
28static int imx8qxp_clk_probe(struct platform_device *pdev)
29{
30 struct device_node *ccm_node = pdev->dev.of_node;
31 const struct imx_clk_scu_rsrc_table *rsrc_table;
30 int ret;
31
32 int ret;
33
32 ret = imx_clk_scu_init(ccm_node);
34 rsrc_table = of_device_get_match_data(&pdev->dev);
35 ret = imx_clk_scu_init(ccm_node, rsrc_table);
33 if (ret)
34 return ret;
35
36 /* ARM core */
37 imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
38
39 /* LSIO SS */
40 imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);

--- 84 unchanged lines hidden (view full) ---

125 if (ret)
126 imx_clk_scu_unregister();
127
128 return ret;
129}
130
131static const struct of_device_id imx8qxp_match[] = {
132 { .compatible = "fsl,scu-clk", },
36 if (ret)
37 return ret;
38
39 /* ARM core */
40 imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
41
42 /* LSIO SS */
43 imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);

--- 84 unchanged lines hidden (view full) ---

128 if (ret)
129 imx_clk_scu_unregister();
130
131 return ret;
132}
133
134static const struct of_device_id imx8qxp_match[] = {
135 { .compatible = "fsl,scu-clk", },
133 { .compatible = "fsl,imx8qxp-clk", },
136 { .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
134 { /* sentinel */ }
135};
136
137static struct platform_driver imx8qxp_clk_driver = {
138 .driver = {
139 .name = "imx8qxp-clk",
140 .of_match_table = imx8qxp_match,
141 .suppress_bind_attrs = true,
142 },
143 .probe = imx8qxp_clk_probe,
144};
145builtin_platform_driver(imx8qxp_clk_driver);
146
147MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
148MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
149MODULE_LICENSE("GPL v2");
137 { /* sentinel */ }
138};
139
140static struct platform_driver imx8qxp_clk_driver = {
141 .driver = {
142 .name = "imx8qxp-clk",
143 .of_match_table = imx8qxp_match,
144 .suppress_bind_attrs = true,
145 },
146 .probe = imx8qxp_clk_probe,
147};
148builtin_platform_driver(imx8qxp_clk_driver);
149
150MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
151MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
152MODULE_LICENSE("GPL v2");