clk-imx8mm.c (715a1284d89a740b197b3bad5eb20d36a397382f) clk-imx8mm.c (c1ae5c6f789acde2ad32226cb5461cc1bc60cdf3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2017-2018 NXP.
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <linux/clk-provider.h>
8#include <linux/err.h>

--- 274 unchanged lines hidden (view full) ---

283
284static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
285
286static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
287 "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
288static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
289 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
290
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2017-2018 NXP.
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <linux/clk-provider.h>
8#include <linux/err.h>

--- 274 unchanged lines hidden (view full) ---

283
284static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
285
286static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
287 "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
288static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
289 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
290
291static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
292 "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
293 "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
294 "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
295
291static struct clk_hw_onecell_data *clk_hw_data;
292static struct clk_hw **hws;
293
294static const int uart_clk_ids[] = {
295 IMX8MM_CLK_UART1_ROOT,
296 IMX8MM_CLK_UART2_ROOT,
297 IMX8MM_CLK_UART3_ROOT,
298 IMX8MM_CLK_UART4_ROOT,

--- 106 unchanged lines hidden (view full) ---

405 hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
406 hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
407 hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
408 hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
409 hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
410 hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
411 hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
412
296static struct clk_hw_onecell_data *clk_hw_data;
297static struct clk_hw **hws;
298
299static const int uart_clk_ids[] = {
300 IMX8MM_CLK_UART1_ROOT,
301 IMX8MM_CLK_UART2_ROOT,
302 IMX8MM_CLK_UART3_ROOT,
303 IMX8MM_CLK_UART4_ROOT,

--- 106 unchanged lines hidden (view full) ---

410 hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
411 hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
412 hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
413 hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
414 hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
415 hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
416 hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
417
418 hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
419 hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
420 hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
421 hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
422 hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
423 hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
424
413 np = dev->of_node;
414 base = devm_platform_ioremap_resource(pdev, 0);
415 if (WARN_ON(IS_ERR(base)))
416 return PTR_ERR(base);
417
418 /* Core Slice */
419 hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
420 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];

--- 243 unchanged lines hidden --- 		425 np = dev->of_node;
426 base = devm_platform_ioremap_resource(pdev, 0);
427 if (WARN_ON(IS_ERR(base)))
428 return PTR_ERR(base);
429
430 /* Core Slice */
431 hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
432 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];

--- 243 unchanged lines hidden ---