| clk-imx27.c (cbecf716ca618fd44feda6bd9a64a8179d031fc5) | clk-imx27.c (379c9a24cc239000b1dec53db02fe17a86947423) |
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| 1// SPDX-License-Identifier: GPL-2.0 2#include <linux/clk.h> 3#include <linux/clk-provider.h> 4#include <linux/clkdev.h> 5#include <linux/err.h> 6#include <linux/io.h> 7#include <linux/of.h> 8#include <linux/of_address.h> --- 35 unchanged lines hidden (view full) --- 44 "32k", "usb_div", "dptc", 45}; 46 47static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; 48 49static struct clk *clk[IMX27_CLK_MAX]; 50static struct clk_onecell_data clk_data; 51 | 1// SPDX-License-Identifier: GPL-2.0 2#include <linux/clk.h> 3#include <linux/clk-provider.h> 4#include <linux/clkdev.h> 5#include <linux/err.h> 6#include <linux/io.h> 7#include <linux/of.h> 8#include <linux/of_address.h> --- 35 unchanged lines hidden (view full) --- 44 "32k", "usb_div", "dptc", 45}; 46 47static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; 48 49static struct clk *clk[IMX27_CLK_MAX]; 50static struct clk_onecell_data clk_data; 51 |
| 52static struct clk ** const uart_clks[] __initconst = { 53 &clk[IMX27_CLK_PER1_GATE], 54 &clk[IMX27_CLK_UART1_IPG_GATE], 55 &clk[IMX27_CLK_UART2_IPG_GATE], 56 &clk[IMX27_CLK_UART3_IPG_GATE], 57 &clk[IMX27_CLK_UART4_IPG_GATE], 58 &clk[IMX27_CLK_UART5_IPG_GATE], 59 &clk[IMX27_CLK_UART6_IPG_GATE], 60 NULL 61}; 62 | |
| 63static void __init _mx27_clocks_init(unsigned long fref) 64{ 65 BUG_ON(!ccm); 66 67 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 68 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); 69 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); 70 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); --- 100 unchanged lines hidden (view full) --- 171 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); 172 173 imx_check_clocks(clk, ARRAY_SIZE(clk)); 174 175 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); 176 177 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); 178 | 52static void __init _mx27_clocks_init(unsigned long fref) 53{ 54 BUG_ON(!ccm); 55 56 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 57 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); 58 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); 59 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); --- 100 unchanged lines hidden (view full) --- 160 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); 161 162 imx_check_clocks(clk, ARRAY_SIZE(clk)); 163 164 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); 165 166 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); 167 |
| 179 imx_register_uart_clocks(uart_clks); | 168 imx_register_uart_clocks(7); |
| 180 181 imx_print_silicon_rev("i.MX27", mx27_revision()); 182} 183 184static void __init mx27_clocks_init_dt(struct device_node *np) 185{ 186 struct device_node *refnp; 187 u32 fref = 26000000; /* default */ --- 20 unchanged lines hidden --- | 169 170 imx_print_silicon_rev("i.MX27", mx27_revision()); 171} 172 173static void __init mx27_clocks_init_dt(struct device_node *np) 174{ 175 struct device_node *refnp; 176 u32 fref = 26000000; /* default */ --- 20 unchanged lines hidden --- |