clk-wm831x.c (ee3e542fec6e69bc9fb668698889a37d93950ddf) | clk-wm831x.c (a5828a6c5f51a909c3c4dbbf22c76c75a033b2e9) |
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1/* 2 * WM831x clock control 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it --- 17 unchanged lines hidden (view full) --- 26 struct clk_hw fll_hw; 27 struct clk_hw clkout_hw; 28 struct clk *xtal; 29 struct clk *fll; 30 struct clk *clkout; 31 bool xtal_ena; 32}; 33 | 1/* 2 * WM831x clock control 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it --- 17 unchanged lines hidden (view full) --- 26 struct clk_hw fll_hw; 27 struct clk_hw clkout_hw; 28 struct clk *xtal; 29 struct clk *fll; 30 struct clk *clkout; 31 bool xtal_ena; 32}; 33 |
34static int wm831x_xtal_is_enabled(struct clk_hw *hw) | 34static int wm831x_xtal_is_prepared(struct clk_hw *hw) |
35{ 36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 37 xtal_hw); 38 39 return clkdata->xtal_ena; 40} 41 42static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw, --- 4 unchanged lines hidden (view full) --- 47 48 if (clkdata->xtal_ena) 49 return 32768; 50 else 51 return 0; 52} 53 54static const struct clk_ops wm831x_xtal_ops = { | 35{ 36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 37 xtal_hw); 38 39 return clkdata->xtal_ena; 40} 41 42static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw, --- 4 unchanged lines hidden (view full) --- 47 48 if (clkdata->xtal_ena) 49 return 32768; 50 else 51 return 0; 52} 53 54static const struct clk_ops wm831x_xtal_ops = { |
55 .is_enabled = wm831x_xtal_is_enabled, | 55 .is_prepared = wm831x_xtal_is_prepared, |
56 .recalc_rate = wm831x_xtal_recalc_rate, 57}; 58 59static struct clk_init_data wm831x_xtal_init = { 60 .name = "xtal", 61 .ops = &wm831x_xtal_ops, 62 .flags = CLK_IS_ROOT, 63}; --- 4 unchanged lines hidden (view full) --- 68 12000000, 69 12288000, 70 19200000, 71 22579600, 72 24000000, 73 24576000, 74}; 75 | 56 .recalc_rate = wm831x_xtal_recalc_rate, 57}; 58 59static struct clk_init_data wm831x_xtal_init = { 60 .name = "xtal", 61 .ops = &wm831x_xtal_ops, 62 .flags = CLK_IS_ROOT, 63}; --- 4 unchanged lines hidden (view full) --- 68 12000000, 69 12288000, 70 19200000, 71 22579600, 72 24000000, 73 24576000, 74}; 75 |
76static int wm831x_fll_is_enabled(struct clk_hw *hw) | 76static int wm831x_fll_is_prepared(struct clk_hw *hw) |
77{ 78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 79 fll_hw); 80 struct wm831x *wm831x = clkdata->wm831x; 81 int ret; 82 83 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1); 84 if (ret < 0) { --- 80 unchanged lines hidden (view full) --- 165 int i; 166 167 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) 168 if (wm831x_fll_auto_rates[i] == rate) 169 break; 170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates)) 171 return -EINVAL; 172 | 77{ 78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 79 fll_hw); 80 struct wm831x *wm831x = clkdata->wm831x; 81 int ret; 82 83 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1); 84 if (ret < 0) { --- 80 unchanged lines hidden (view full) --- 165 int i; 166 167 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) 168 if (wm831x_fll_auto_rates[i] == rate) 169 break; 170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates)) 171 return -EINVAL; 172 |
173 if (wm831x_fll_is_enabled(hw)) | 173 if (wm831x_fll_is_prepared(hw)) |
174 return -EPERM; 175 176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2, 177 WM831X_FLL_AUTO_FREQ_MASK, i); 178} 179 180static const char *wm831x_fll_parents[] = { 181 "xtal", --- 33 unchanged lines hidden (view full) --- 215 default: 216 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n", 217 ret & WM831X_FLL_CLK_SRC_MASK); 218 return 0; 219 } 220} 221 222static const struct clk_ops wm831x_fll_ops = { | 174 return -EPERM; 175 176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2, 177 WM831X_FLL_AUTO_FREQ_MASK, i); 178} 179 180static const char *wm831x_fll_parents[] = { 181 "xtal", --- 33 unchanged lines hidden (view full) --- 215 default: 216 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n", 217 ret & WM831X_FLL_CLK_SRC_MASK); 218 return 0; 219 } 220} 221 222static const struct clk_ops wm831x_fll_ops = { |
223 .is_enabled = wm831x_fll_is_enabled, | 223 .is_prepared = wm831x_fll_is_prepared, |
224 .prepare = wm831x_fll_prepare, 225 .unprepare = wm831x_fll_unprepare, 226 .round_rate = wm831x_fll_round_rate, 227 .recalc_rate = wm831x_fll_recalc_rate, 228 .set_rate = wm831x_fll_set_rate, 229 .get_parent = wm831x_fll_get_parent, 230}; 231 232static struct clk_init_data wm831x_fll_init = { 233 .name = "fll", 234 .ops = &wm831x_fll_ops, 235 .parent_names = wm831x_fll_parents, 236 .num_parents = ARRAY_SIZE(wm831x_fll_parents), 237 .flags = CLK_SET_RATE_GATE, 238}; 239 | 224 .prepare = wm831x_fll_prepare, 225 .unprepare = wm831x_fll_unprepare, 226 .round_rate = wm831x_fll_round_rate, 227 .recalc_rate = wm831x_fll_recalc_rate, 228 .set_rate = wm831x_fll_set_rate, 229 .get_parent = wm831x_fll_get_parent, 230}; 231 232static struct clk_init_data wm831x_fll_init = { 233 .name = "fll", 234 .ops = &wm831x_fll_ops, 235 .parent_names = wm831x_fll_parents, 236 .num_parents = ARRAY_SIZE(wm831x_fll_parents), 237 .flags = CLK_SET_RATE_GATE, 238}; 239 |
240static int wm831x_clkout_is_enabled(struct clk_hw *hw) | 240static int wm831x_clkout_is_prepared(struct clk_hw *hw) |
241{ 242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 243 clkout_hw); 244 struct wm831x *wm831x = clkdata->wm831x; 245 int ret; 246 247 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); 248 if (ret < 0) { --- 81 unchanged lines hidden (view full) --- 330 struct wm831x *wm831x = clkdata->wm831x; 331 332 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, 333 WM831X_CLKOUT_SRC, 334 parent << WM831X_CLKOUT_SRC_SHIFT); 335} 336 337static const struct clk_ops wm831x_clkout_ops = { | 241{ 242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, 243 clkout_hw); 244 struct wm831x *wm831x = clkdata->wm831x; 245 int ret; 246 247 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); 248 if (ret < 0) { --- 81 unchanged lines hidden (view full) --- 330 struct wm831x *wm831x = clkdata->wm831x; 331 332 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, 333 WM831X_CLKOUT_SRC, 334 parent << WM831X_CLKOUT_SRC_SHIFT); 335} 336 337static const struct clk_ops wm831x_clkout_ops = { |
338 .is_enabled = wm831x_clkout_is_enabled, | 338 .is_prepared = wm831x_clkout_is_prepared, |
339 .prepare = wm831x_clkout_prepare, 340 .unprepare = wm831x_clkout_unprepare, 341 .get_parent = wm831x_clkout_get_parent, 342 .set_parent = wm831x_clkout_set_parent, 343}; 344 345static struct clk_init_data wm831x_clkout_init = { 346 .name = "clkout", --- 66 unchanged lines hidden --- | 339 .prepare = wm831x_clkout_prepare, 340 .unprepare = wm831x_clkout_unprepare, 341 .get_parent = wm831x_clkout_get_parent, 342 .set_parent = wm831x_clkout_set_parent, 343}; 344 345static struct clk_init_data wm831x_clkout_init = { 346 .name = "clkout", --- 66 unchanged lines hidden --- |