| clk-plldig.c (db865ee447d46eccd641dc70c7f9acc231a3141e) | clk-plldig.c (0d152f2db535c207d1ea5bee62ff889f9d850a25) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 NXP 4 * 5 * Clock driver for LS1028A Display output interfaces(LCD, DPHY). 6 */ 7 8#include <linux/clk-provider.h> --- 23 unchanged lines hidden (view full) --- 32#define PLLDIG_REG_PLLCAL1 0x38 33#define PLLDIG_REG_PLLCAL2 0x3c 34 35/* Range of the VCO frequencies, in Hz */ 36#define PLLDIG_MIN_VCO_FREQ 650000000 37#define PLLDIG_MAX_VCO_FREQ 1300000000 38 39/* Range of the output frequencies, in Hz */ | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 NXP 4 * 5 * Clock driver for LS1028A Display output interfaces(LCD, DPHY). 6 */ 7 8#include <linux/clk-provider.h> --- 23 unchanged lines hidden (view full) --- 32#define PLLDIG_REG_PLLCAL1 0x38 33#define PLLDIG_REG_PLLCAL2 0x3c 34 35/* Range of the VCO frequencies, in Hz */ 36#define PLLDIG_MIN_VCO_FREQ 650000000 37#define PLLDIG_MAX_VCO_FREQ 1300000000 38 39/* Range of the output frequencies, in Hz */ |
| 40#define PHI1_MIN_FREQ 27000000 41#define PHI1_MAX_FREQ 600000000 | 40#define PHI1_MIN_FREQ 27000000UL 41#define PHI1_MAX_FREQ 600000000UL |
| 42 43/* Maximum value of the reduced frequency divider */ 44#define MAX_RFDPHI1 63UL 45 46/* Best value of multiplication factor divider */ 47#define PLLDIG_DEFAULT_MFD 44 48 49/* --- 237 unchanged lines hidden --- | 42 43/* Maximum value of the reduced frequency divider */ 44#define MAX_RFDPHI1 63UL 45 46/* Best value of multiplication factor divider */ 47#define PLLDIG_DEFAULT_MFD 44 48 49/* --- 237 unchanged lines hidden --- |