clk-bcm2835.c (6d18b8adbe679b5947aa822b676efff230acc5f6) clk-bcm2835.c (cfbab8fbab9c330aca963095a439c451ac97c0dd)
1/*
2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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802 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
803 .parents = bcm2835_clock_per_parents,
804 .ctl_reg = CM_EMMCCTL,
805 .div_reg = CM_EMMCDIV,
806 .int_bits = 4,
807 .frac_bits = 8,
808};
809
1/*
2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.

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802 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
803 .parents = bcm2835_clock_per_parents,
804 .ctl_reg = CM_EMMCCTL,
805 .div_reg = CM_EMMCDIV,
806 .int_bits = 4,
807 .frac_bits = 8,
808};
809
810static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
811 .name = "pwm",
812 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
813 .parents = bcm2835_clock_per_parents,
814 .ctl_reg = CM_PWMCTL,
815 .div_reg = CM_PWMDIV,
816 .int_bits = 12,
817 .frac_bits = 12,
818};
819
810struct bcm2835_pll {
811 struct clk_hw hw;
812 struct bcm2835_cprman *cprman;
813 const struct bcm2835_pll_data *data;
814};
815
816static int bcm2835_pll_is_on(struct clk_hw *hw)
817{

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1579 * non-stop vpu clock.
1580 */
1581 clks[BCM2835_CLOCK_PERI_IMAGE] =
1582 clk_register_gate(dev, "peri_image", "vpu",
1583 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1584 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1585 0, &cprman->regs_lock);
1586
820struct bcm2835_pll {
821 struct clk_hw hw;
822 struct bcm2835_cprman *cprman;
823 const struct bcm2835_pll_data *data;
824};
825
826static int bcm2835_pll_is_on(struct clk_hw *hw)
827{

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1589 * non-stop vpu clock.
1590 */
1591 clks[BCM2835_CLOCK_PERI_IMAGE] =
1592 clk_register_gate(dev, "peri_image", "vpu",
1593 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1594 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1595 0, &cprman->regs_lock);
1596
1597 clks[BCM2835_CLOCK_PWM] =
1598 bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
1599
1587 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1588 &cprman->onecell);
1589}
1590
1591static const struct of_device_id bcm2835_clk_of_match[] = {
1592 { .compatible = "brcm,bcm2835-cprman", },
1593 {}
1594};

--- 15 unchanged lines hidden --- 		1600 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1601 &cprman->onecell);
1602}
1603
1604static const struct of_device_id bcm2835_clk_of_match[] = {
1605 { .compatible = "brcm,bcm2835-cprman", },
1606 {}
1607};

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