| clk-bcm2835.c (33b689600f43094a9316a1b582f2286d17bc737b) | clk-bcm2835.c (728436956aa172b24a3212295f8b53feb6479f32) |
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| 1/* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. --- 1357 unchanged lines hidden (view full) --- 1366 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1367 .name = "plla_per", 1368 .source_pll = "plla", 1369 .cm_reg = CM_PLLA, 1370 .a2w_reg = A2W_PLLA_PER, 1371 .load_mask = CM_PLLA_LOADPER, 1372 .hold_mask = CM_PLLA_HOLDPER, 1373 .fixed_divider = 1), | 1/* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. --- 1357 unchanged lines hidden (view full) --- 1366 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1367 .name = "plla_per", 1368 .source_pll = "plla", 1369 .cm_reg = CM_PLLA, 1370 .a2w_reg = A2W_PLLA_PER, 1371 .load_mask = CM_PLLA_LOADPER, 1372 .hold_mask = CM_PLLA_HOLDPER, 1373 .fixed_divider = 1), |
| 1374 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1375 .name = "plla_dsi0", 1376 .source_pll = "plla", 1377 .cm_reg = CM_PLLA, 1378 .a2w_reg = A2W_PLLA_DSI0, 1379 .load_mask = CM_PLLA_LOADDSI0, 1380 .hold_mask = CM_PLLA_HOLDDSI0, 1381 .fixed_divider = 1), 1382 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1383 .name = "plla_ccp2", 1384 .source_pll = "plla", 1385 .cm_reg = CM_PLLA, 1386 .a2w_reg = A2W_PLLA_CCP2, 1387 .load_mask = CM_PLLA_LOADCCP2, 1388 .hold_mask = CM_PLLA_HOLDCCP2, 1389 .fixed_divider = 1), |
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| 1374 1375 /* PLLB is used for the ARM's clock. */ 1376 [BCM2835_PLLB] = REGISTER_PLL( 1377 .name = "pllb", 1378 .cm_ctrl_reg = CM_PLLB, 1379 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1380 .frac_reg = A2W_PLLB_FRAC, 1381 .ana_reg_base = A2W_PLLB_ANA0, --- 98 unchanged lines hidden (view full) --- 1480 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1481 .name = "plld_per", 1482 .source_pll = "plld", 1483 .cm_reg = CM_PLLD, 1484 .a2w_reg = A2W_PLLD_PER, 1485 .load_mask = CM_PLLD_LOADPER, 1486 .hold_mask = CM_PLLD_HOLDPER, 1487 .fixed_divider = 1), | 1390 1391 /* PLLB is used for the ARM's clock. */ 1392 [BCM2835_PLLB] = REGISTER_PLL( 1393 .name = "pllb", 1394 .cm_ctrl_reg = CM_PLLB, 1395 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1396 .frac_reg = A2W_PLLB_FRAC, 1397 .ana_reg_base = A2W_PLLB_ANA0, --- 98 unchanged lines hidden (view full) --- 1496 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1497 .name = "plld_per", 1498 .source_pll = "plld", 1499 .cm_reg = CM_PLLD, 1500 .a2w_reg = A2W_PLLD_PER, 1501 .load_mask = CM_PLLD_LOADPER, 1502 .hold_mask = CM_PLLD_HOLDPER, 1503 .fixed_divider = 1), |
| 1504 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1505 .name = "plld_dsi0", 1506 .source_pll = "plld", 1507 .cm_reg = CM_PLLD, 1508 .a2w_reg = A2W_PLLD_DSI0, 1509 .load_mask = CM_PLLD_LOADDSI0, 1510 .hold_mask = CM_PLLD_HOLDDSI0, 1511 .fixed_divider = 1), 1512 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1513 .name = "plld_dsi1", 1514 .source_pll = "plld", 1515 .cm_reg = CM_PLLD, 1516 .a2w_reg = A2W_PLLD_DSI1, 1517 .load_mask = CM_PLLD_LOADDSI1, 1518 .hold_mask = CM_PLLD_HOLDDSI1, 1519 .fixed_divider = 1), |
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| 1488 1489 /* 1490 * PLLH is used to supply the pixel clock or the AUX clock for the 1491 * TV encoder. 1492 * 1493 * It is in the HDMI power domain. 1494 */ 1495 [BCM2835_PLLH] = REGISTER_PLL( --- 233 unchanged lines hidden --- | 1520 1521 /* 1522 * PLLH is used to supply the pixel clock or the AUX clock for the 1523 * TV encoder. 1524 * 1525 * It is in the HDMI power domain. 1526 */ 1527 [BCM2835_PLLH] = REGISTER_PLL( --- 233 unchanged lines hidden --- |