ivpu_mmu.c (aa66c93d5f69d48809468c4e2124e408e31fa931) ivpu_mmu.c (2c3801b17459da806f44d3f63f89e999f23e9e60)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#include <linux/circ_buf.h>
7#include <linux/highmem.h>
8

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514 int ret;
515
516 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC);
517
518 ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0);
519 if (ret)
520 return ret;
521
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#include <linux/circ_buf.h>
7#include <linux/highmem.h>
8

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514 int ret;
515
516 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC);
517
518 ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0);
519 if (ret)
520 return ret;
521
522 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
522 if (!ivpu_is_force_snoop_enabled(vdev))
523 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
523 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
524
525 ret = ivpu_mmu_cmdq_wait_for_cons(vdev);
526 if (ret) {
527 u32 err;
528
529 val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS);
530 err = REG_GET_FLD(IVPU_MMU_REG_CMDQ_CONS, ERR, val);

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562
563static int ivpu_mmu_reset(struct ivpu_device *vdev)
564{
565 struct ivpu_mmu_info *mmu = vdev->mmu;
566 u32 val;
567 int ret;
568
569 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);
524 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
525
526 ret = ivpu_mmu_cmdq_wait_for_cons(vdev);
527 if (ret) {
528 u32 err;
529
530 val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS);
531 err = REG_GET_FLD(IVPU_MMU_REG_CMDQ_CONS, ERR, val);

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563
564static int ivpu_mmu_reset(struct ivpu_device *vdev)
565{
566 struct ivpu_mmu_info *mmu = vdev->mmu;
567 u32 val;
568 int ret;
569
570 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);
570 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);
571 if (!ivpu_is_force_snoop_enabled(vdev))
572 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);
571 mmu->cmdq.prod = 0;
572 mmu->cmdq.cons = 0;
573
574 memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE);
575 mmu->evtq.prod = 0;
576 mmu->evtq.cons = 0;
577
578 ret = ivpu_mmu_reg_write_cr0(vdev, 0);

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656 FIELD_PREP(IVPU_MMU_STE_1_STRW, IVPU_MMU_STE_1_STRW_NSEL1) |
657 FIELD_PREP(IVPU_MMU_STE_1_CONT, IVPU_MMU_STRTAB_CFG_LOG2SIZE) |
658 IVPU_MMU_STE_1_MEV |
659 IVPU_MMU_STE_1_S1STALLD;
660
661 WRITE_ONCE(entry[1], str[1]);
662 WRITE_ONCE(entry[0], str[0]);
663
573 mmu->cmdq.prod = 0;
574 mmu->cmdq.cons = 0;
575
576 memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE);
577 mmu->evtq.prod = 0;
578 mmu->evtq.cons = 0;
579
580 ret = ivpu_mmu_reg_write_cr0(vdev, 0);

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658 FIELD_PREP(IVPU_MMU_STE_1_STRW, IVPU_MMU_STE_1_STRW_NSEL1) |
659 FIELD_PREP(IVPU_MMU_STE_1_CONT, IVPU_MMU_STRTAB_CFG_LOG2SIZE) |
660 IVPU_MMU_STE_1_MEV |
661 IVPU_MMU_STE_1_S1STALLD;
662
663 WRITE_ONCE(entry[1], str[1]);
664 WRITE_ONCE(entry[0], str[0]);
665
664 clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE);
666 if (!ivpu_is_force_snoop_enabled(vdev))
667 clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE);
665
666 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
667}
668
669static int ivpu_mmu_strtab_init(struct ivpu_device *vdev)
670{
671 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID0);
672 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID3);

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730 memset(cd, 0, sizeof(cd));
731 }
732
733 WRITE_ONCE(entry[1], cd[1]);
734 WRITE_ONCE(entry[2], cd[2]);
735 WRITE_ONCE(entry[3], cd[3]);
736 WRITE_ONCE(entry[0], cd[0]);
737
668
669 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
670}
671
672static int ivpu_mmu_strtab_init(struct ivpu_device *vdev)
673{
674 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID0);
675 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID3);

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733 memset(cd, 0, sizeof(cd));
734 }
735
736 WRITE_ONCE(entry[1], cd[1]);
737 WRITE_ONCE(entry[2], cd[2]);
738 WRITE_ONCE(entry[3], cd[3]);
739 WRITE_ONCE(entry[0], cd[0]);
740
738 clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);
741 if (!ivpu_is_force_snoop_enabled(vdev))
742 clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);
739
740 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
741 cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]);
742
743 mutex_lock(&mmu->lock);
744 if (!mmu->on)
745 goto unlock;
746

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744 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
745 cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]);
746
747 mutex_lock(&mmu->lock);
748 if (!mmu->on)
749 goto unlock;
750

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