aie2_pci.h (ac49797c1815d4f8f04b7053b2998c546283c89e) aie2_pci.h (aac243092b707bb3018e951d470cc1a9bcbaba6c)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _AIE2_PCI_H_
7#define _AIE2_PCI_H_
8
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _AIE2_PCI_H_
7#define _AIE2_PCI_H_
8
9#include <linux/semaphore.h>
10
9#include "amdxdna_mailbox.h"
10
11#define AIE2_INTERVAL 20000 /* us */
12#define AIE2_TIMEOUT 1000000 /* us */
13
14/* Firmware determines device memory base address and size */
15#define AIE2_DEVM_BASE 0x4000000
16#define AIE2_DEVM_SIZE SZ_64M

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71 PSP_ARG2_REG,
72 PSP_NUM_IN_REGS, /* number of input registers */
73 PSP_INTR_REG = PSP_NUM_IN_REGS,
74 PSP_STATUS_REG,
75 PSP_RESP_REG,
76 PSP_MAX_REGS /* Keep this at the end */
77};
78
11#include "amdxdna_mailbox.h"
12
13#define AIE2_INTERVAL 20000 /* us */
14#define AIE2_TIMEOUT 1000000 /* us */
15
16/* Firmware determines device memory base address and size */
17#define AIE2_DEVM_BASE 0x4000000
18#define AIE2_DEVM_SIZE SZ_64M

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73 PSP_ARG2_REG,
74 PSP_NUM_IN_REGS, /* number of input registers */
75 PSP_INTR_REG = PSP_NUM_IN_REGS,
76 PSP_STATUS_REG,
77 PSP_RESP_REG,
78 PSP_MAX_REGS /* Keep this at the end */
79};
80
81struct amdxdna_client;
79struct amdxdna_fw_ver;
80struct amdxdna_hwctx;
82struct amdxdna_fw_ver;
83struct amdxdna_hwctx;
84struct amdxdna_sched_job;
81
82struct psp_config {
83 const void *fw_buf;
84 u32 fw_size;
85 void __iomem *psp_regs[PSP_MAX_REGS];
86};
87
88struct aie_version {

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113 u32 freq_mhz;
114};
115
116struct rt_config {
117 u32 type;
118 u32 value;
119};
120
85
86struct psp_config {
87 const void *fw_buf;
88 u32 fw_size;
89 void __iomem *psp_regs[PSP_MAX_REGS];
90};
91
92struct aie_version {

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117 u32 freq_mhz;
118};
119
120struct rt_config {
121 u32 type;
122 u32 value;
123};
124
125/*
126 * Define the maximum number of pending commands in a hardware context.
127 * Must be power of 2!
128 */
129#define HWCTX_MAX_CMDS 4
130#define get_job_idx(seq) ((seq) & (HWCTX_MAX_CMDS - 1))
121struct amdxdna_hwctx_priv {
122 struct amdxdna_gem_obj *heap;
123 void *mbox_chann;
131struct amdxdna_hwctx_priv {
132 struct amdxdna_gem_obj *heap;
133 void *mbox_chann;
134
135 struct drm_gpu_scheduler sched;
136 struct drm_sched_entity entity;
137
138 struct mutex io_lock; /* protect seq and cmd order */
139 struct wait_queue_head job_free_wq;
140 u32 num_pending;
141 u64 seq;
142 struct semaphore job_sem;
143 bool job_done;
144
145 /* Completed job counter */
146 u64 completed;
147
148 struct amdxdna_gem_obj *cmd_buf[HWCTX_MAX_CMDS];
149 struct drm_syncobj *syncobj;
124};
125
126struct amdxdna_dev_hdl {
127 struct amdxdna_dev *xdna;
128 const struct amdxdna_dev_priv *priv;
129 void __iomem *sram_base;
130 void __iomem *smu_base;
131 void __iomem *mbox_base;

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194int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version);
195int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata);
196int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
197 struct amdxdna_fw_ver *fw_ver);
198int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
199int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
200int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size);
201int aie2_config_cu(struct amdxdna_hwctx *hwctx);
150};
151
152struct amdxdna_dev_hdl {
153 struct amdxdna_dev *xdna;
154 const struct amdxdna_dev_priv *priv;
155 void __iomem *sram_base;
156 void __iomem *smu_base;
157 void __iomem *mbox_base;

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220int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version);
221int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata);
222int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
223 struct amdxdna_fw_ver *fw_ver);
224int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
225int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
226int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size);
227int aie2_config_cu(struct amdxdna_hwctx *hwctx);
228int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
229 int (*notify_cb)(void *, const u32 *, size_t));
230int aie2_cmdlist_single_execbuf(struct amdxdna_hwctx *hwctx,
231 struct amdxdna_sched_job *job,
232 int (*notify_cb)(void *, const u32 *, size_t));
233int aie2_cmdlist_multi_execbuf(struct amdxdna_hwctx *hwctx,
234 struct amdxdna_sched_job *job,
235 int (*notify_cb)(void *, const u32 *, size_t));
236int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
237 int (*notify_cb)(void *, const u32 *, size_t));
202
203/* aie2_hwctx.c */
204int aie2_hwctx_init(struct amdxdna_hwctx *hwctx);
205void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx);
206int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
238
239/* aie2_hwctx.c */
240int aie2_hwctx_init(struct amdxdna_hwctx *hwctx);
241void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx);
242int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
243int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
244void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
245void aie2_restart_ctx(struct amdxdna_client *client);
207
208#endif /* _AIE2_PCI_H_ */
246
247#endif /* _AIE2_PCI_H_ */