perf_event.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) perf_event.c (687eb3c42f4ad81e7c947c50e2d865f692064291)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xtensa Performance Monitor Module driver
4 * See Tensilica Debug User's Guide for PMU registers documentation.
5 *
6 * Copyright (C) 2015 Cadence Design Systems Inc.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/irqdomain.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/perf_event.h>
14#include <linux/platform_device.h>
15
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xtensa Performance Monitor Module driver
4 * See Tensilica Debug User's Guide for PMU registers documentation.
5 *
6 * Copyright (C) 2015 Cadence Design Systems Inc.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/irqdomain.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/perf_event.h>
14#include <linux/platform_device.h>
15
16#include <asm/core.h>
16#include <asm/processor.h>
17#include <asm/stacktrace.h>
18
17#include <asm/processor.h>
18#include <asm/stacktrace.h>
19
20#define XTENSA_HWVERSION_RG_2015_0 260000
21
22#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0
23#define XTENSA_PMU_ERI_BASE 0x00101000
24#else
25#define XTENSA_PMU_ERI_BASE 0x00001000
26#endif
27
19/* Global control/status for all perf counters */
28/* Global control/status for all perf counters */
20#define XTENSA_PMU_PMG 0x1000
29#define XTENSA_PMU_PMG XTENSA_PMU_ERI_BASE
21/* Perf counter values */
30/* Perf counter values */
22#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4)
31#define XTENSA_PMU_PM(i) (XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4)
23/* Perf counter control registers */
32/* Perf counter control registers */
24#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4)
33#define XTENSA_PMU_PMCTRL(i) (XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4)
25/* Perf counter status registers */
34/* Perf counter status registers */
26#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4)
35#define XTENSA_PMU_PMSTAT(i) (XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4)
27
28#define XTENSA_PMU_PMG_PMEN 0x1
29
30#define XTENSA_PMU_COUNTER_MASK 0xffffffffULL
31#define XTENSA_PMU_COUNTER_MAX 0x7fffffff
32
33#define XTENSA_PMU_PMCTRL_INTEN 0x00000001
34#define XTENSA_PMU_PMCTRL_KRNLCNT 0x00000008

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37#define XTENSA_PMU_PMG_PMEN 0x1
38
39#define XTENSA_PMU_COUNTER_MASK 0xffffffffULL
40#define XTENSA_PMU_COUNTER_MAX 0x7fffffff
41
42#define XTENSA_PMU_PMCTRL_INTEN 0x00000001
43#define XTENSA_PMU_PMCTRL_KRNLCNT 0x00000008

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