| vmenter.S (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) | vmenter.S (a149180fbcf336e97ce4eb2cdc13672727feb94d) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2#include <linux/linkage.h> 3#include <asm/asm.h> 4#include <asm/bitsperlong.h> 5#include <asm/kvm_vcpu_regs.h> 6#include <asm/nospec-branch.h> 7 8#define WORD_SIZE (BITS_PER_LONG / 8) --- 97 unchanged lines hidden (view full) --- 106 mov %r11, VCPU_R11(%_ASM_AX) 107 mov %r12, VCPU_R12(%_ASM_AX) 108 mov %r13, VCPU_R13(%_ASM_AX) 109 mov %r14, VCPU_R14(%_ASM_AX) 110 mov %r15, VCPU_R15(%_ASM_AX) 111#endif 112 113 /* | 1/* SPDX-License-Identifier: GPL-2.0 */ 2#include <linux/linkage.h> 3#include <asm/asm.h> 4#include <asm/bitsperlong.h> 5#include <asm/kvm_vcpu_regs.h> 6#include <asm/nospec-branch.h> 7 8#define WORD_SIZE (BITS_PER_LONG / 8) --- 97 unchanged lines hidden (view full) --- 106 mov %r11, VCPU_R11(%_ASM_AX) 107 mov %r12, VCPU_R12(%_ASM_AX) 108 mov %r13, VCPU_R13(%_ASM_AX) 109 mov %r14, VCPU_R14(%_ASM_AX) 110 mov %r15, VCPU_R15(%_ASM_AX) 111#endif 112 113 /* |
| 114 * Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be 115 * untrained as soon as we exit the VM and are back to the 116 * kernel. This should be done before re-enabling interrupts 117 * because interrupt handlers won't sanitize 'ret' if the return is 118 * from the kernel. 119 */ 120 UNTRAIN_RET 121 122 /* |
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| 114 * Clear all general purpose registers except RSP and RAX to prevent 115 * speculative use of the guest's values, even those that are reloaded 116 * via the stack. In theory, an L1 cache miss when restoring registers 117 * could lead to speculative execution with the guest's values. 118 * Zeroing XORs are dirt cheap, i.e. the extra paranoia is essentially 119 * free. RSP and RAX are exempt as they are restored by hardware 120 * during VM-Exit. 121 */ --- 63 unchanged lines hidden (view full) --- 185 1862: cli 187 188#ifdef CONFIG_RETPOLINE 189 /* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */ 190 FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE 191#endif 192 | 123 * Clear all general purpose registers except RSP and RAX to prevent 124 * speculative use of the guest's values, even those that are reloaded 125 * via the stack. In theory, an L1 cache miss when restoring registers 126 * could lead to speculative execution with the guest's values. 127 * Zeroing XORs are dirt cheap, i.e. the extra paranoia is essentially 128 * free. RSP and RAX are exempt as they are restored by hardware 129 * during VM-Exit. 130 */ --- 63 unchanged lines hidden (view full) --- 194 1952: cli 196 197#ifdef CONFIG_RETPOLINE 198 /* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */ 199 FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE 200#endif 201 |
| 202 /* 203 * Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be 204 * untrained as soon as we exit the VM and are back to the 205 * kernel. This should be done before re-enabling interrupts 206 * because interrupt handlers won't sanitize RET if the return is 207 * from the kernel. 208 */ 209 UNTRAIN_RET 210 |
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| 193 pop %_ASM_BX 194 195#ifdef CONFIG_X86_64 196 pop %r12 197 pop %r13 198 pop %r14 199 pop %r15 200#else --- 13 unchanged lines hidden --- | 211 pop %_ASM_BX 212 213#ifdef CONFIG_X86_64 214 pop %r12 215 pop %r13 216 pop %r14 217 pop %r15 218#else --- 13 unchanged lines hidden --- |