cpuid.h (4f2c0a4acffbec01079c28f839422e64ddeff004) cpuid.h (5f6e839ebc951c50f1ca06791d016c256f0285a9)
1/******************************************************************************
2 * arch-x86/cpuid.h
3 *
4 * CPUID interface to Xen.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the

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84 * EDX: guest tsc incarnation (migration count)
85 * Sub-leaf 1: EAX: tsc offset low part
86 * EBX: tsc offset high part
87 * ECX: multiplicator for tsc->ns conversion
88 * EDX: shift amount for tsc->ns conversion
89 * Sub-leaf 2: EAX: host tsc frequency in kHz
90 */
91
1/******************************************************************************
2 * arch-x86/cpuid.h
3 *
4 * CPUID interface to Xen.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the

--- 75 unchanged lines hidden (view full) ---

84 * EDX: guest tsc incarnation (migration count)
85 * Sub-leaf 1: EAX: tsc offset low part
86 * EBX: tsc offset high part
87 * ECX: multiplicator for tsc->ns conversion
88 * EDX: shift amount for tsc->ns conversion
89 * Sub-leaf 2: EAX: host tsc frequency in kHz
90 */
91
92#define XEN_CPUID_TSC_EMULATED (1u << 0)
93#define XEN_CPUID_HOST_TSC_RELIABLE (1u << 1)
94#define XEN_CPUID_RDTSCP_INSTR_AVAIL (1u << 2)
95
96#define XEN_CPUID_TSC_MODE_DEFAULT (0)
97#define XEN_CPUID_TSC_MODE_ALWAYS_EMULATE (1u)
98#define XEN_CPUID_TSC_MODE_NEVER_EMULATE (2u)
99#define XEN_CPUID_TSC_MODE_PVRDTSCP (3u)
100
92/*
93 * Leaf 5 (0x40000x04)
94 * HVM-specific features
95 * Sub-leaf 0: EAX: Features
96 * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag)
101/*
102 * Leaf 5 (0x40000x04)
103 * HVM-specific features
104 * Sub-leaf 0: EAX: Features
105 * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag)
106 * Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag)
97 */
98#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
99#define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1) /* Virtualized x2APIC accesses */
100/* Memory mapped from other domains has valid IOMMU entries */
101#define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2)
102#define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */
103#define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */
104/*
107 */
108#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
109#define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1) /* Virtualized x2APIC accesses */
110/* Memory mapped from other domains has valid IOMMU entries */
111#define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2)
112#define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */
113#define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */
114/*
105 * Bits 55:49 from the IO-APIC RTE and bits 11:5 from the MSI address can be
106 * used to store high bits for the Destination ID. This expands the Destination
107 * ID field from 8 to 15 bits, allowing to target APIC IDs up 32768.
115 * With interrupt format set to 0 (non-remappable) bits 55:49 from the
116 * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
117 * high bits for the Destination ID. This expands the Destination ID
118 * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
108 */
109#define XEN_HVM_CPUID_EXT_DEST_ID (1u << 5)
119 */
120#define XEN_HVM_CPUID_EXT_DEST_ID (1u << 5)
110/* Per-vCPU event channel upcalls */
121/*
122 * Per-vCPU event channel upcalls work correctly with physical IRQs
123 * bound to event channels.
124 */
111#define XEN_HVM_CPUID_UPCALL_VECTOR (1u << 6)
112
113/*
114 * Leaf 6 (0x40000x05)
115 * PV-specific parameters
116 * Sub-leaf 0: EAX: max available sub-leaf
117 * Sub-leaf 0: EBX: bits 0-7: max machine address width
118 */
119
120/* Max. address width in bits taking memory hotplug into account. */
121#define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0)
122
123#define XEN_CPUID_MAX_NUM_LEAVES 5
124
125#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
125#define XEN_HVM_CPUID_UPCALL_VECTOR (1u << 6)
126
127/*
128 * Leaf 6 (0x40000x05)
129 * PV-specific parameters
130 * Sub-leaf 0: EAX: max available sub-leaf
131 * Sub-leaf 0: EBX: bits 0-7: max machine address width
132 */
133
134/* Max. address width in bits taking memory hotplug into account. */
135#define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0)
136
137#define XEN_CPUID_MAX_NUM_LEAVES 5
138
139#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */