pgtable-3level.h (9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) pgtable-3level.h (ea4654e0885348f0faa47f6d7b44a08d75ad16e9)
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H
4
5/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs.
8 *

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47
48static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
49{
50 pxx_xchg64(pmd, pmdp, native_pmd_val(pmd));
51}
52
53static inline void native_set_pud(pud_t *pudp, pud_t pud)
54{
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H
4
5/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs.
8 *

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47
48static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
49{
50 pxx_xchg64(pmd, pmdp, native_pmd_val(pmd));
51}
52
53static inline void native_set_pud(pud_t *pudp, pud_t pud)
54{
55#ifdef CONFIG_PAGE_TABLE_ISOLATION
55#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
56 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
57#endif
58 pxx_xchg64(pud, pudp, native_pud_val(pud));
59}
60
61/*
62 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
63 * entry, so clear the bottom half first and enforce ordering with a compiler

--- 146 unchanged lines hidden --- 		56 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
57#endif
58 pxx_xchg64(pud, pudp, native_pud_val(pud));
59}
60
61/*
62 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
63 * entry, so clear the bottom half first and enforce ordering with a compiler

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