| cpufeatures.h (159013a7ca18c271ff64192deb62a689b622d860) | cpufeatures.h (8754e67ad4ac692c67ff1f99c0d07156f04ae40c) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_CPUFEATURES_H 3#define _ASM_X86_CPUFEATURES_H 4 5/* 6 * Defines x86 CPU feature bits 7 */ 8#define NCAPINTS 22 /* N 32-bit words worth of info */ --- 467 unchanged lines hidden (view full) --- 476#define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* Clear branch history at syscall entry using SW loop */ 477#define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ 478#define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ 479#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ 480#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ 481#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ 482#define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ 483#define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to downclocking */ | 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_CPUFEATURES_H 3#define _ASM_X86_CPUFEATURES_H 4 5/* 6 * Defines x86 CPU feature bits 7 */ 8#define NCAPINTS 22 /* N 32-bit words worth of info */ --- 467 unchanged lines hidden (view full) --- 476#define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* Clear branch history at syscall entry using SW loop */ 477#define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ 478#define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ 479#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ 480#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ 481#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ 482#define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ 483#define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to downclocking */ |
| 484#define X86_FEATURE_INDIRECT_THUNK_ITS (21*32 + 9) /* Use thunk for indirect branches in lower half of cacheline */ |
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| 484 485/* 486 * BUG word(s) 487 */ 488#define X86_BUG(x) (NCAPINTS*32 + (x)) 489 490#define X86_BUG_F00F X86_BUG(0) /* "f00f" Intel F00F */ 491#define X86_BUG_FDIV X86_BUG(1) /* "fdiv" FPU FDIV */ --- 46 unchanged lines hidden --- | 485 486/* 487 * BUG word(s) 488 */ 489#define X86_BUG(x) (NCAPINTS*32 + (x)) 490 491#define X86_BUG_F00F X86_BUG(0) /* "f00f" Intel F00F */ 492#define X86_BUG_FDIV X86_BUG(1) /* "fdiv" FPU FDIV */ --- 46 unchanged lines hidden --- |