init_64.c (9938b04472d5c59f8bd8152a548533a8599596a2) init_64.c (c5b8b5beee1e2aadef0409dba555b7085d57910d)
1/*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/module.h>

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1764 case SUN4V_CHIP_SPARC64X:
1765 case SUN4V_CHIP_SPARC_M6:
1766 /* T4 and later support 52-bit virtual addresses. */
1767 sparc64_va_hole_top = 0xfff8000000000000UL;
1768 sparc64_va_hole_bottom = 0x0008000000000000UL;
1769 max_phys_bits = 47;
1770 break;
1771 case SUN4V_CHIP_SPARC_M7:
1/*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/module.h>

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1764 case SUN4V_CHIP_SPARC64X:
1765 case SUN4V_CHIP_SPARC_M6:
1766 /* T4 and later support 52-bit virtual addresses. */
1767 sparc64_va_hole_top = 0xfff8000000000000UL;
1768 sparc64_va_hole_bottom = 0x0008000000000000UL;
1769 max_phys_bits = 47;
1770 break;
1771 case SUN4V_CHIP_SPARC_M7:
1772 case SUN4V_CHIP_SPARC_SN:
1772 default:
1773 /* M7 and later support 52-bit virtual addresses. */
1774 sparc64_va_hole_top = 0xfff8000000000000UL;
1775 sparc64_va_hole_bottom = 0x0008000000000000UL;
1776 max_phys_bits = 49;
1777 break;
1778 }
1779 }

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1981{
1982 unsigned long pagecv_flag;
1983
1984 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1985 * enables MCD error. Do not set bit 9 on M7 processor.
1986 */
1987 switch (sun4v_chip_type) {
1988 case SUN4V_CHIP_SPARC_M7:
1773 default:
1774 /* M7 and later support 52-bit virtual addresses. */
1775 sparc64_va_hole_top = 0xfff8000000000000UL;
1776 sparc64_va_hole_bottom = 0x0008000000000000UL;
1777 max_phys_bits = 49;
1778 break;
1779 }
1780 }

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1982{
1983 unsigned long pagecv_flag;
1984
1985 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1986 * enables MCD error. Do not set bit 9 on M7 processor.
1987 */
1988 switch (sun4v_chip_type) {
1989 case SUN4V_CHIP_SPARC_M7:
1990 case SUN4V_CHIP_SPARC_SN:
1989 pagecv_flag = 0x00;
1990 break;
1991 default:
1992 pagecv_flag = _PAGE_CV_4V;
1993 break;
1994 }
1995#ifndef CONFIG_DEBUG_PAGEALLOC
1996 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {

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2133 * later. Kernel does not run with MCD enabled and hence rest
2134 * of the required steps to fully configure memory corruption
2135 * detection are not taken. We need to ensure TTE.mcde is not
2136 * set on M7 processor. Compute the value of cacheability
2137 * flag for use later taking this into consideration.
2138 */
2139 switch (sun4v_chip_type) {
2140 case SUN4V_CHIP_SPARC_M7:
1991 pagecv_flag = 0x00;
1992 break;
1993 default:
1994 pagecv_flag = _PAGE_CV_4V;
1995 break;
1996 }
1997#ifndef CONFIG_DEBUG_PAGEALLOC
1998 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {

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2135 * later. Kernel does not run with MCD enabled and hence rest
2136 * of the required steps to fully configure memory corruption
2137 * detection are not taken. We need to ensure TTE.mcde is not
2138 * set on M7 processor. Compute the value of cacheability
2139 * flag for use later taking this into consideration.
2140 */
2141 switch (sun4v_chip_type) {
2142 case SUN4V_CHIP_SPARC_M7:
2143 case SUN4V_CHIP_SPARC_SN:
2141 page_cache4v_flag = _PAGE_CP_4V;
2142 break;
2143 default:
2144 page_cache4v_flag = _PAGE_CACHE_4V;
2145 break;
2146 }
2147
2148 if (tlb_type == hypervisor)

--- 801 unchanged lines hidden --- 		2144 page_cache4v_flag = _PAGE_CP_4V;
2145 break;
2146 default:
2147 page_cache4v_flag = _PAGE_CACHE_4V;
2148 break;
2149 }
2150
2151 if (tlb_type == hypervisor)

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