| trampoline_32.S (5a2dd72abdae75ea2960145e0549635ce4e0be96) | trampoline_32.S (8401707ff645521e9f21cbb8fe3b138f60e85680) |
|---|---|
| 1/* 2 * trampoline.S: SMP cpu boot-up trampoline code. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8#include <linux/init.h> 9#include <asm/head.h> 10#include <asm/psr.h> 11#include <asm/page.h> 12#include <asm/asi.h> 13#include <asm/ptrace.h> 14#include <asm/vaddrs.h> 15#include <asm/contregs.h> 16#include <asm/thread_info.h> 17 | 1/* 2 * trampoline.S: SMP cpu boot-up trampoline code. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8#include <linux/init.h> 9#include <asm/head.h> 10#include <asm/psr.h> 11#include <asm/page.h> 12#include <asm/asi.h> 13#include <asm/ptrace.h> 14#include <asm/vaddrs.h> 15#include <asm/contregs.h> 16#include <asm/thread_info.h> 17 |
| 18 .globl sun4m_cpu_startup, __smp4m_processor_id | 18 .globl sun4m_cpu_startup, __smp4m_processor_id, __leon_processor_id |
| 19 .globl sun4d_cpu_startup, __smp4d_processor_id 20 21 __CPUINIT 22 .align 4 23 24/* When we start up a cpu for the first time it enters this routine. 25 * This initializes the chip from whatever state the prom left it 26 * in and sets PIL in %psr to 15, no irqs. --- 74 unchanged lines hidden (view full) --- 101 retl 102 mov %g1, %o7 103 104__smp4d_processor_id: 105 lda [%g0] ASI_M_VIKING_TMP1, %g2 106 retl 107 mov %g1, %o7 108 | 19 .globl sun4d_cpu_startup, __smp4d_processor_id 20 21 __CPUINIT 22 .align 4 23 24/* When we start up a cpu for the first time it enters this routine. 25 * This initializes the chip from whatever state the prom left it 26 * in and sets PIL in %psr to 15, no irqs. --- 74 unchanged lines hidden (view full) --- 101 retl 102 mov %g1, %o7 103 104__smp4d_processor_id: 105 lda [%g0] ASI_M_VIKING_TMP1, %g2 106 retl 107 mov %g1, %o7 108 |
| 109__leon_processor_id: 110 rd %asr17,%g2 111 srl %g2,28,%g2 112 retl 113 mov %g1, %o7 114 |
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| 109/* CPUID in bootbus can be found at PA 0xff0140000 */ 110#define SUN4D_BOOTBUS_CPUID 0xf0140000 111 112 __CPUINIT 113 .align 4 114 115sun4d_cpu_startup: 116 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ --- 38 unchanged lines hidden (view full) --- 155 call %g5 156 nop 157 158 /* Start this processor. */ 159 call smp4d_callin 160 nop 161 162 b,a smp_do_cpu_idle | 115/* CPUID in bootbus can be found at PA 0xff0140000 */ 116#define SUN4D_BOOTBUS_CPUID 0xf0140000 117 118 __CPUINIT 119 .align 4 120 121sun4d_cpu_startup: 122 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ --- 38 unchanged lines hidden (view full) --- 161 call %g5 162 nop 163 164 /* Start this processor. */ 165 call smp4d_callin 166 nop 167 168 b,a smp_do_cpu_idle |
| 169 170#ifdef CONFIG_SPARC_LEON 171 172 __CPUINIT 173 .align 4 174 .global leon_smp_cpu_startup, smp_penguin_ctable 175 176leon_smp_cpu_startup: 177 178 set smp_penguin_ctable,%g1 179 ld [%g1+4],%g1 180 srl %g1,4,%g1 181 set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */ 182 sta %g1, [%g5] ASI_M_MMUREGS 183 184 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ 185 set (PSR_PIL | PSR_S | PSR_PS), %g1 186 wr %g1, 0x0, %psr ! traps off though 187 WRITE_PAUSE 188 189 /* Our %wim is one behind CWP */ 190 mov 2, %g1 191 wr %g1, 0x0, %wim 192 WRITE_PAUSE 193 194 /* Set tbr - we use just one trap table. */ 195 set trapbase, %g1 196 wr %g1, 0x0, %tbr 197 WRITE_PAUSE 198 199 /* Get our CPU id */ 200 rd %asr17,%g3 201 202 /* Give ourselves a stack and curptr. */ 203 set current_set, %g5 204 srl %g3, 28, %g4 205 sll %g4, 2, %g4 206 ld [%g5 + %g4], %g6 207 208 sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp 209 or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp 210 add %g6, %sp, %sp 211 212 /* Turn on traps (PSR_ET). */ 213 rd %psr, %g1 214 wr %g1, PSR_ET, %psr ! traps on 215 WRITE_PAUSE 216 217 /* Init our caches, etc. */ 218 set poke_srmmu, %g5 219 ld [%g5], %g5 220 call %g5 221 nop 222 223 /* Start this processor. */ 224 call leon_callin 225 nop 226 227 b,a smp_do_cpu_idle 228 229#endif |
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