dma-mapping.h (ee664a9252d24ef10317d1bba8fc8f4c6495b36c) dma-mapping.h (451d7400a34cb679369e337d67f0238ed410f484)
1#ifndef ___ASM_SPARC_DMA_MAPPING_H
2#define ___ASM_SPARC_DMA_MAPPING_H
3
4#include <linux/scatterlist.h>
5#include <linux/mm.h>
6#include <linux/dma-debug.h>
7
8#define DMA_ERROR_CODE (~(dma_addr_t)0x0)

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27}
28
29#include <asm-generic/dma-mapping-common.h>
30
31static inline void *dma_alloc_coherent(struct device *dev, size_t size,
32 dma_addr_t *dma_handle, gfp_t flag)
33{
34 struct dma_map_ops *ops = get_dma_ops(dev);
1#ifndef ___ASM_SPARC_DMA_MAPPING_H
2#define ___ASM_SPARC_DMA_MAPPING_H
3
4#include <linux/scatterlist.h>
5#include <linux/mm.h>
6#include <linux/dma-debug.h>
7
8#define DMA_ERROR_CODE (~(dma_addr_t)0x0)

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27}
28
29#include <asm-generic/dma-mapping-common.h>
30
31static inline void *dma_alloc_coherent(struct device *dev, size_t size,
32 dma_addr_t *dma_handle, gfp_t flag)
33{
34 struct dma_map_ops *ops = get_dma_ops(dev);
35 void *cpu_addr;
35
36
36 return ops->alloc_coherent(dev, size, dma_handle, flag);
37 cpu_addr = ops->alloc_coherent(dev, size, dma_handle, flag);
38 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
39 return cpu_addr;
37}
38
39static inline void dma_free_coherent(struct device *dev, size_t size,
40 void *cpu_addr, dma_addr_t dma_handle)
41{
42 struct dma_map_ops *ops = get_dma_ops(dev);
43
40}
41
42static inline void dma_free_coherent(struct device *dev, size_t size,
43 void *cpu_addr, dma_addr_t dma_handle)
44{
45 struct dma_map_ops *ops = get_dma_ops(dev);
46
47 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
44 ops->free_coherent(dev, size, cpu_addr, dma_handle);
45}
46
47static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
48{
49 return (dma_addr == DMA_ERROR_CODE);
50}
51
52static inline int dma_get_cache_alignment(void)
53{
54 /*
55 * no easy way to get cache size on all processors, so return
56 * the maximum possible, to be safe
57 */
58 return (1 << INTERNODE_CACHE_SHIFT);
59}
60
61#endif
48 ops->free_coherent(dev, size, cpu_addr, dma_handle);
49}
50
51static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
52{
53 return (dma_addr == DMA_ERROR_CODE);
54}
55
56static inline int dma_get_cache_alignment(void)
57{
58 /*
59 * no easy way to get cache size on all processors, so return
60 * the maximum possible, to be safe
61 */
62 return (1 << INTERNODE_CACHE_SHIFT);
63}
64
65#endif