| pci-sh7751.h (fc8e1ead9314cf0e0f1922e661428b93d3a50d88) | pci-sh7751.h (25985edcedea6396277003854657b5f3cb31a628) |
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| 1/* 2 * Low-Level PCI Support for SH7751 targets 3 * 4 * Dustin McIntire (dustin@sensoria.com) (c) 2001 5 * Paul Mundt (lethal@linux-sh.org) (c) 2003 6 * 7 * May be copied or modified under the terms of the GNU General Public 8 * License. See linux/COPYING for more information. --- 47 unchanged lines hidden (view full) --- 56 #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */ 57 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 58 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 59 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 60#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 61 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 62 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 63 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ | 1/* 2 * Low-Level PCI Support for SH7751 targets 3 * 4 * Dustin McIntire (dustin@sensoria.com) (c) 2001 5 * Paul Mundt (lethal@linux-sh.org) (c) 2003 6 * 7 * May be copied or modified under the terms of the GNU General Public 8 * License. See linux/COPYING for more information. --- 47 unchanged lines hidden (view full) --- 56 #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */ 57 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 58 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 59 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 60#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 61 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 62 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 63 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ |
| 64 #define SH7751_PCICONF3_HD7 0x00800000 /* Single Funtion device */ | 64 #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */ |
| 65 #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */ 66 #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */ 67 #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */ 68#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */ 69 #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */ 70 #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */ 71#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */ 72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ --- 57 unchanged lines hidden --- | 65 #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */ 66 #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */ 67 #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */ 68#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */ 69 #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */ 70 #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */ 71#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */ 72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ --- 57 unchanged lines hidden --- |