ap.h (d710d370c4911e83da5d2bc43d4a2c3b56bd27e7) ap.h (2d6c0008be64bd813008d2a796108e89edec1030)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Adjunct processor (AP) interfaces
4 *
5 * Copyright IBM Corp. 2017
6 *
7 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
8 * Martin Schwidefsky <schwidefsky@de.ibm.com>

--- 49 unchanged lines hidden (view full) ---

58{
59 unsigned long reg0 = AP_MKQID(0, 0);
60 unsigned long reg1 = 0;
61
62 asm volatile(
63 " lgr 0,%[reg0]\n" /* qid into gr0 */
64 " lghi 1,0\n" /* 0 into gr1 */
65 " lghi 2,0\n" /* 0 into gr2 */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Adjunct processor (AP) interfaces
4 *
5 * Copyright IBM Corp. 2017
6 *
7 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
8 * Martin Schwidefsky <schwidefsky@de.ibm.com>

--- 49 unchanged lines hidden (view full) ---

58{
59 unsigned long reg0 = AP_MKQID(0, 0);
60 unsigned long reg1 = 0;
61
62 asm volatile(
63 " lgr 0,%[reg0]\n" /* qid into gr0 */
64 " lghi 1,0\n" /* 0 into gr1 */
65 " lghi 2,0\n" /* 0 into gr2 */
66 " .long 0xb2af0000\n" /* PQAP(TAPQ) */
66 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
67 "0: la %[reg1],1\n" /* 1 into reg1 */
68 "1:\n"
69 EX_TABLE(0b, 1b)
70 : [reg1] "+&d" (reg1)
71 : [reg0] "d" (reg0)
72 : "cc", "0", "1", "2");
73 return reg1 != 0;
74}

--- 8 unchanged lines hidden (view full) ---

83static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
84{
85 struct ap_queue_status reg1;
86 unsigned long reg2;
87
88 asm volatile(
89 " lgr 0,%[qid]\n" /* qid into gr0 */
90 " lghi 2,0\n" /* 0 into gr2 */
67 "0: la %[reg1],1\n" /* 1 into reg1 */
68 "1:\n"
69 EX_TABLE(0b, 1b)
70 : [reg1] "+&d" (reg1)
71 : [reg0] "d" (reg0)
72 : "cc", "0", "1", "2");
73 return reg1 != 0;
74}

--- 8 unchanged lines hidden (view full) ---

83static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
84{
85 struct ap_queue_status reg1;
86 unsigned long reg2;
87
88 asm volatile(
89 " lgr 0,%[qid]\n" /* qid into gr0 */
90 " lghi 2,0\n" /* 0 into gr2 */
91 " .long 0xb2af0000\n" /* PQAP(TAPQ) */
91 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
92 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
93 " lgr %[reg2],2\n" /* gr2 into reg2 */
94 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2)
95 : [qid] "d" (qid)
96 : "cc", "0", "1", "2");
97 if (info)
98 *info = reg2;
99 return reg1;

--- 24 unchanged lines hidden (view full) ---

124 */
125static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
126{
127 unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */
128 struct ap_queue_status reg1;
129
130 asm volatile(
131 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
92 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
93 " lgr %[reg2],2\n" /* gr2 into reg2 */
94 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2)
95 : [qid] "d" (qid)
96 : "cc", "0", "1", "2");
97 if (info)
98 *info = reg2;
99 return reg1;

--- 24 unchanged lines hidden (view full) ---

124 */
125static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
126{
127 unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */
128 struct ap_queue_status reg1;
129
130 asm volatile(
131 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
132 " .long 0xb2af0000\n" /* PQAP(RAPQ) */
132 " .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
133 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
134 : [reg1] "=&d" (reg1)
135 : [reg0] "d" (reg0)
136 : "cc", "0", "1");
137 return reg1;
138}
139
140/**

--- 4 unchanged lines hidden (view full) ---

145 */
146static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
147{
148 unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */
149 struct ap_queue_status reg1;
150
151 asm volatile(
152 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
133 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
134 : [reg1] "=&d" (reg1)
135 : [reg0] "d" (reg0)
136 : "cc", "0", "1");
137 return reg1;
138}
139
140/**

--- 4 unchanged lines hidden (view full) ---

145 */
146static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
147{
148 unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */
149 struct ap_queue_status reg1;
150
151 asm volatile(
152 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
153 " .long 0xb2af0000\n" /* PQAP(ZAPQ) */
153 " .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
154 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
155 : [reg1] "=&d" (reg1)
156 : [reg0] "d" (reg0)
157 : "cc", "0", "1");
158 return reg1;
159}
160
161/**

--- 25 unchanged lines hidden (view full) ---

187{
188 unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */
189 unsigned long reg1 = -EOPNOTSUPP;
190 struct ap_config_info *reg2 = config;
191
192 asm volatile(
193 " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
194 " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
154 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
155 : [reg1] "=&d" (reg1)
156 : [reg0] "d" (reg0)
157 : "cc", "0", "1");
158 return reg1;
159}
160
161/**

--- 25 unchanged lines hidden (view full) ---

187{
188 unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */
189 unsigned long reg1 = -EOPNOTSUPP;
190 struct ap_config_info *reg2 = config;
191
192 asm volatile(
193 " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
194 " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
195 " .long 0xb2af0000\n" /* PQAP(QCI) */
195 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */
196 "0: la %[reg1],0\n" /* good case, QCI fc available */
197 "1:\n"
198 EX_TABLE(0b, 1b)
199 : [reg1] "+&d" (reg1)
200 : [reg0] "d" (reg0), [reg2] "d" (reg2)
201 : "cc", "memory", "0", "2");
202
203 return reg1;

--- 40 unchanged lines hidden (view full) ---

244 unsigned long reg2 = virt_to_phys(ind);
245
246 reg1.qirqctrl = qirqctrl;
247
248 asm volatile(
249 " lgr 0,%[reg0]\n" /* qid param into gr0 */
250 " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
251 " lgr 2,%[reg2]\n" /* ni addr into gr2 */
196 "0: la %[reg1],0\n" /* good case, QCI fc available */
197 "1:\n"
198 EX_TABLE(0b, 1b)
199 : [reg1] "+&d" (reg1)
200 : [reg0] "d" (reg0), [reg2] "d" (reg2)
201 : "cc", "memory", "0", "2");
202
203 return reg1;

--- 40 unchanged lines hidden (view full) ---

244 unsigned long reg2 = virt_to_phys(ind);
245
246 reg1.qirqctrl = qirqctrl;
247
248 asm volatile(
249 " lgr 0,%[reg0]\n" /* qid param into gr0 */
250 " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
251 " lgr 2,%[reg2]\n" /* ni addr into gr2 */
252 " .long 0xb2af0000\n" /* PQAP(AQIC) */
252 " .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
253 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
254 : [reg1] "+&d" (reg1)
255 : [reg0] "d" (reg0), [reg2] "d" (reg2)
256 : "cc", "0", "1", "2");
257
258 return reg1.status;
259}
260

--- 33 unchanged lines hidden (view full) ---

294 } reg1;
295 unsigned long reg2;
296
297 reg1.value = apinfo->val;
298
299 asm volatile(
300 " lgr 0,%[reg0]\n" /* qid param into gr0 */
301 " lgr 1,%[reg1]\n" /* qact in info into gr1 */
253 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
254 : [reg1] "+&d" (reg1)
255 : [reg0] "d" (reg0), [reg2] "d" (reg2)
256 : "cc", "0", "1", "2");
257
258 return reg1.status;
259}
260

--- 33 unchanged lines hidden (view full) ---

294 } reg1;
295 unsigned long reg2;
296
297 reg1.value = apinfo->val;
298
299 asm volatile(
300 " lgr 0,%[reg0]\n" /* qid param into gr0 */
301 " lgr 1,%[reg1]\n" /* qact in info into gr1 */
302 " .long 0xb2af0000\n" /* PQAP(QACT) */
302 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
303 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
304 " lgr %[reg2],2\n" /* qact out info into reg2 */
305 : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2)
306 : [reg0] "d" (reg0)
307 : "cc", "0", "1", "2");
308 apinfo->val = reg2;
309 return reg1.status;
310}

--- 131 unchanged lines hidden --- 		303 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
304 " lgr %[reg2],2\n" /* qact out info into reg2 */
305 : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2)
306 : [reg0] "d" (reg0)
307 : "cc", "0", "1", "2");
308 apinfo->val = reg2;
309 return reg1.status;
310}

--- 131 unchanged lines hidden ---