| vector.c (36ec807b627b4c0a0a382f0ae48eac7187d14b2b) | vector.c (d1703dc7bc8ec7adb91f5ceaf1556ff1ed212858) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2023 SiFive 4 * Author: Andy Chiu <andy.chiu@sifive.com> 5 */ 6#include <linux/export.h> 7#include <linux/sched/signal.h> 8#include <linux/types.h> --- 52 unchanged lines hidden (view full) --- 61 0, riscv_v_vsize, NULL); 62#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 63 riscv_v_kernel_cachep = kmem_cache_create("riscv_vector_kctx", 64 riscv_v_vsize, 16, 65 SLAB_PANIC, NULL); 66#endif 67} 68 | 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2023 SiFive 4 * Author: Andy Chiu <andy.chiu@sifive.com> 5 */ 6#include <linux/export.h> 7#include <linux/sched/signal.h> 8#include <linux/types.h> --- 52 unchanged lines hidden (view full) --- 61 0, riscv_v_vsize, NULL); 62#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 63 riscv_v_kernel_cachep = kmem_cache_create("riscv_vector_kctx", 64 riscv_v_vsize, 16, 65 SLAB_PANIC, NULL); 66#endif 67} 68 |
| 69static bool insn_is_vector(u32 insn_buf) | 69bool insn_is_vector(u32 insn_buf) |
| 70{ 71 u32 opcode = insn_buf & __INSN_OPCODE_MASK; 72 u32 width, csr; 73 74 /* 75 * All V-related instructions, including CSR operations are 4-Byte. So, 76 * do not handle if the instruction length is not 4-Byte. 77 */ --- 239 unchanged lines hidden --- | 70{ 71 u32 opcode = insn_buf & __INSN_OPCODE_MASK; 72 u32 width, csr; 73 74 /* 75 * All V-related instructions, including CSR operations are 4-Byte. So, 76 * do not handle if the instruction length is not 4-Byte. 77 */ --- 239 unchanged lines hidden --- |