sys_hwprobe.c (3fd6c59042dbba50391e30862beac979491145fe) sys_hwprobe.c (d1703dc7bc8ec7adb91f5ceaf1556ff1ed212858)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * The hwprobe interface, for allowing userspace to probe to see which features
4 * are supported by the hardware. See Documentation/arch/riscv/hwprobe.rst for
5 * more details.
6 */
7#include <linux/syscalls.h>
8#include <asm/cacheflush.h>

--- 187 unchanged lines hidden (view full) ---

196
197 if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())
198 return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
199
200 return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
201}
202#endif
203
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * The hwprobe interface, for allowing userspace to probe to see which features
4 * are supported by the hardware. See Documentation/arch/riscv/hwprobe.rst for
5 * more details.
6 */
7#include <linux/syscalls.h>
8#include <asm/cacheflush.h>

--- 187 unchanged lines hidden (view full) ---

196
197 if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())
198 return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
199
200 return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
201}
202#endif
203
204#ifdef CONFIG_RISCV_VECTOR_MISALIGNED
205static u64 hwprobe_vec_misaligned(const struct cpumask *cpus)
206{
207 int cpu;
208 u64 perf = -1ULL;
209
210 /* Return if supported or not even if speed wasn't probed */
211 for_each_cpu(cpu, cpus) {
212 int this_perf = per_cpu(vector_misaligned_access, cpu);
213
214 if (perf == -1ULL)
215 perf = this_perf;
216
217 if (perf != this_perf) {
218 perf = RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN;
219 break;
220 }
221 }
222
223 if (perf == -1ULL)
224 return RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN;
225
226 return perf;
227}
228#else
229static u64 hwprobe_vec_misaligned(const struct cpumask *cpus)
230{
231 return RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN;
232}
233#endif
234
204static void hwprobe_one_pair(struct riscv_hwprobe *pair,
205 const struct cpumask *cpus)
206{
207 switch (pair->key) {
208 case RISCV_HWPROBE_KEY_MVENDORID:
209 case RISCV_HWPROBE_KEY_MARCHID:
210 case RISCV_HWPROBE_KEY_MIMPID:
211 hwprobe_arch_id(pair, cpus);

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224 hwprobe_isa_ext0(pair, cpus);
225 break;
226
227 case RISCV_HWPROBE_KEY_CPUPERF_0:
228 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
229 pair->value = hwprobe_misaligned(cpus);
230 break;
231
235static void hwprobe_one_pair(struct riscv_hwprobe *pair,
236 const struct cpumask *cpus)
237{
238 switch (pair->key) {
239 case RISCV_HWPROBE_KEY_MVENDORID:
240 case RISCV_HWPROBE_KEY_MARCHID:
241 case RISCV_HWPROBE_KEY_MIMPID:
242 hwprobe_arch_id(pair, cpus);

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255 hwprobe_isa_ext0(pair, cpus);
256 break;
257
258 case RISCV_HWPROBE_KEY_CPUPERF_0:
259 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
260 pair->value = hwprobe_misaligned(cpus);
261 break;
262
263 case RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF:
264 pair->value = hwprobe_vec_misaligned(cpus);
265 break;
266
232 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
233 pair->value = 0;
234 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
235 pair->value = riscv_cboz_block_size;
236 break;
237 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
238 pair->value = user_max_virt_addr();
239 break;

--- 211 unchanged lines hidden --- 		267 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
268 pair->value = 0;
269 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
270 pair->value = riscv_cboz_block_size;
271 break;
272 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
273 pair->value = user_max_virt_addr();
274 break;

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