smpboot.c (f557af081de6b45a25e27d633b4d8d2dbc2f428e) smpboot.c (eabd9db64ea8ba64d2a0b1d70da38e1a95dcd08b)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SMP initialisation and IPI support
4 * Based on arch/arm64/kernel/smp.c
5 *
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2015 Regents of the University of California
8 * Copyright (C) 2017 SiFive

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91 if (hart == INVALID_HARTID) {
92 pr_warn("Invalid hartid\n");
93 return 0;
94 }
95
96 if (hart == cpuid_to_hartid_map(0)) {
97 BUG_ON(found_boot_cpu);
98 found_boot_cpu = true;
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SMP initialisation and IPI support
4 * Based on arch/arm64/kernel/smp.c
5 *
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2015 Regents of the University of California
8 * Copyright (C) 2017 SiFive

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91 if (hart == INVALID_HARTID) {
92 pr_warn("Invalid hartid\n");
93 return 0;
94 }
95
96 if (hart == cpuid_to_hartid_map(0)) {
97 BUG_ON(found_boot_cpu);
98 found_boot_cpu = true;
99 early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count));
100 return 0;
101 }
102
103 if (cpu_count >= NR_CPUS) {
104 pr_warn("NR_CPUS is too small for the number of ACPI tables.\n");
105 return 0;
106 }
107
108 cpuid_to_hartid_map(cpu_count) = hart;
99 return 0;
100 }
101
102 if (cpu_count >= NR_CPUS) {
103 pr_warn("NR_CPUS is too small for the number of ACPI tables.\n");
104 return 0;
105 }
106
107 cpuid_to_hartid_map(cpu_count) = hart;
109 early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count));
110 cpu_count++;
111
112 return 0;
113}
114
115static void __init acpi_parse_and_init_cpus(void)
116{
117 acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0);

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209/*
210 * C entry point for a secondary processor.
211 */
212asmlinkage __visible void smp_callin(void)
213{
214 struct mm_struct *mm = &init_mm;
215 unsigned int curr_cpuid = smp_processor_id();
216
108 cpu_count++;
109
110 return 0;
111}
112
113static void __init acpi_parse_and_init_cpus(void)
114{
115 acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0);

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207/*
208 * C entry point for a secondary processor.
209 */
210asmlinkage __visible void smp_callin(void)
211{
212 struct mm_struct *mm = &init_mm;
213 unsigned int curr_cpuid = smp_processor_id();
214
217 if (has_vector()) {
218 /*
219 * Return as early as possible so the hart with a mismatching
220 * vlen won't boot.
221 */
222 if (riscv_v_setup_vsize())
223 return;
224 }
225
226 /* All kernel threads share the same mm context. */
227 mmgrab(mm);
228 current->active_mm = mm;
229
230 store_cpu_topology(curr_cpuid);
231 notify_cpu_starting(curr_cpuid);
232
233 riscv_ipi_enable();
234
235 numa_add_cpu(curr_cpuid);
236 set_cpu_online(curr_cpuid, true);
237
215 /* All kernel threads share the same mm context. */
216 mmgrab(mm);
217 current->active_mm = mm;
218
219 store_cpu_topology(curr_cpuid);
220 notify_cpu_starting(curr_cpuid);
221
222 riscv_ipi_enable();
223
224 numa_add_cpu(curr_cpuid);
225 set_cpu_online(curr_cpuid, true);
226
227 if (has_vector()) {
228 if (riscv_v_setup_vsize())
229 elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
230 }
231
238 riscv_user_isa_enable();
239
240 /*
241 * Remote cache and TLB flushes are ignored while the CPU is offline,
242 * so flush them both right now just in case.
243 */
244 local_flush_icache_all();
245 local_flush_tlb_all();
246 complete(&cpu_running);
247 /*
248 * Disable preemption before enabling interrupts, so we don't try to
249 * schedule a CPU that hasn't actually started yet.
250 */
251 local_irq_enable();
252 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
253}
232 riscv_user_isa_enable();
233
234 /*
235 * Remote cache and TLB flushes are ignored while the CPU is offline,
236 * so flush them both right now just in case.
237 */
238 local_flush_icache_all();
239 local_flush_tlb_all();
240 complete(&cpu_running);
241 /*
242 * Disable preemption before enabling interrupts, so we don't try to
243 * schedule a CPU that hasn't actually started yet.
244 */
245 local_irq_enable();
246 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
247}