cpu.c (8916c9054f940acbd735e33067e8a7e5a06f8834) cpu.c (1631ba1259d6d7f49b6028f2a1a0fa02be1c522a)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6#include <linux/init.h>
7#include <linux/seq_file.h>
8#include <linux/of.h>
9#include <asm/hwcap.h>
10#include <asm/smp.h>
11#include <asm/pgtable.h>
12
13/*
14 * Returns the hart ID of the given device tree node, or -ENODEV if the node
15 * isn't an enabled and valid RISC-V hart node.
16 */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6#include <linux/init.h>
7#include <linux/seq_file.h>
8#include <linux/of.h>
9#include <asm/hwcap.h>
10#include <asm/smp.h>
11#include <asm/pgtable.h>
12
13/*
14 * Returns the hart ID of the given device tree node, or -ENODEV if the node
15 * isn't an enabled and valid RISC-V hart node.
16 */
17int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
17int riscv_of_processor_hartid(struct device_node *node)
18{
19 const char *isa;
18{
19 const char *isa;
20 u32 hart;
20
21 if (!of_device_is_compatible(node, "riscv")) {
22 pr_warn("Found incompatible CPU\n");
23 return -ENODEV;
24 }
25
21
22 if (!of_device_is_compatible(node, "riscv")) {
23 pr_warn("Found incompatible CPU\n");
24 return -ENODEV;
25 }
26
26 *hart = (unsigned long) of_get_cpu_hwid(node, 0);
27 if (*hart == ~0UL) {
27 hart = of_get_cpu_hwid(node, 0);
28 if (hart == ~0U) {
28 pr_warn("Found CPU without hart ID\n");
29 return -ENODEV;
30 }
31
32 if (!of_device_is_available(node)) {
29 pr_warn("Found CPU without hart ID\n");
30 return -ENODEV;
31 }
32
33 if (!of_device_is_available(node)) {
33 pr_info("CPU with hartid=%lu is not available\n", *hart);
34 pr_info("CPU with hartid=%d is not available\n", hart);
34 return -ENODEV;
35 }
36
37 if (of_property_read_string(node, "riscv,isa", &isa)) {
35 return -ENODEV;
36 }
37
38 if (of_property_read_string(node, "riscv,isa", &isa)) {
38 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
39 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
39 return -ENODEV;
40 }
41 if (isa[0] != 'r' || isa[1] != 'v') {
40 return -ENODEV;
41 }
42 if (isa[0] != 'r' || isa[1] != 'v') {
42 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
43 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
43 return -ENODEV;
44 }
45
44 return -ENODEV;
45 }
46
46 return 0;
47 return hart;
47}
48
49/*
50 * Find hart ID of the CPU DT node under which given DT node falls.
51 *
52 * To achieve this, we walk up the DT tree until we find an active
53 * RISC-V core (HART) node and extract the cpuid from it.
54 */
48}
49
50/*
51 * Find hart ID of the CPU DT node under which given DT node falls.
52 *
53 * To achieve this, we walk up the DT tree until we find an active
54 * RISC-V core (HART) node and extract the cpuid from it.
55 */
55int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
56int riscv_of_parent_hartid(struct device_node *node)
56{
57{
57 int rc;
58
59 for (; node; node = node->parent) {
58 for (; node; node = node->parent) {
60 if (of_device_is_compatible(node, "riscv")) {
61 rc = riscv_of_processor_hartid(node, hartid);
62 if (!rc)
63 return 0;
64 }
59 if (of_device_is_compatible(node, "riscv"))
60 return riscv_of_processor_hartid(node);
65 }
66
67 return -1;
68}
69
70#ifdef CONFIG_PROC_FS
71#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
72 { \

--- 15 unchanged lines hidden (view full) ---

88 * alphabetically.
89 * 4. Non-standard extensions (starts with 'X') must be listed after all
90 * standard extensions. They must be separated from other multi-letter
91 * extensions by an underscore.
92 */
93static struct riscv_isa_ext_data isa_ext_arr[] = {
94 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
95 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
61 }
62
63 return -1;
64}
65
66#ifdef CONFIG_PROC_FS
67#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
68 { \

--- 15 unchanged lines hidden (view full) ---

84 * alphabetically.
85 * 4. Non-standard extensions (starts with 'X') must be listed after all
86 * standard extensions. They must be separated from other multi-letter
87 * extensions by an underscore.
88 */
89static struct riscv_isa_ext_data isa_ext_arr[] = {
90 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
91 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
92 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
96 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
97};
98
99static void print_isa_ext(struct seq_file *f)
100{
101 struct riscv_isa_ext_data *edata;
102 int i = 0, arr_sz;
103

--- 105 unchanged lines hidden --- 		93 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
94};
95
96static void print_isa_ext(struct seq_file *f)
97{
98 struct riscv_isa_ext_data *edata;
99 int i = 0, arr_sz;
100

--- 105 unchanged lines hidden ---